A side-channel attack (SCA) hardened AES-128 and RSA crypto-processor in 14-nm CMOS with measured resistance to correlation power/electromagnetic analysis (CPA/CEMA) in both time and frequency domains is demonstrated. While previously reported linear low-dropout regulators (LDOs) offer improvements in minimum-time-to-disclose (MTD) of extracted key bytes in the time domain, their transformations are less effective against frequency-domain attacks. This article describes a non-linear digital LDO (NL-DLDO) with control loop randomizations that bolster SCA resistance in the frequency domain. The NL-DLDO cascaded with an AES engine augmented with arithmetic countermeasures enables $>250\text{K}\times $ improvement in MTD, with no CPA/CEMA/DNN attacks detected after 1-B encryptions, with 8% power and 10% area overheads incurred by arithmetic techniques. The RSA-4K crypto-processor implements exponent magnitude and timing randomizations along with dynamic memory addressing to mitigate time- and frequency-domain attacks. The countermeasures enable $711\times $ suppression in means separation in current/EM magnitudes from 3.1 mV to $4.35~\mu \text{V}$ , reducing attacker’s accuracy to an ineffective random guess classification, while limiting area and performance overheads to < 0.05% and 3.25%, respectively.

中文翻译：

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14纳米CMOS中的时/频域侧通道抗攻击AES-128和RSA-4K加密处理器

演示了在14纳米CMOS中对AES-128和RSA加密处理器进行了加固的侧通道攻击（SCA），在时域和频域中均具有对相关功率/电磁分析（CPA / CEMA）的测量电阻。尽管先前报道的线性低压差稳压器（LDO）可以在时域中提高提取的关键字节的最短披露时间（MTD），但其转换对频域攻击的效果较差。本文介绍了一种非线性数字LDO（NL-DLDO），它具有控制环随机化功能，可在频域中增强SCA电阻。NL-DLDO与AES引擎级联，并增强了算术对策 $> 250 \ text {K} \ times $ MTD的改进，1-B加密后未检测到CPA / CEMA / DNN攻击，算术技术产生了8％的功耗和10％的面积开销。RSA-4K加密处理器可实现指数幅度和时序随机化以及动态内存寻址，以减轻时域和频域攻击。对策使 $ 711 \次$ 抑制意味着电流/ EM幅度从3.1 mV分离到 $ 4.35〜\ mu \ text {V} $ ，将攻击者的准确性降低为无效的随机猜测分类，同时将区域和性能开销分别限制为<0.05％和3.25％。