An 8-bit 1-GS/s asynchronous loop-unrolled (LU) successive approximation register (SAR)-Flash hybrid analog-to-digital converter (ADC) with complementary dynamic amplifiers (CDAs) is presented. The proposed ADC is a combination of an asynchronous LU-SAR ADC and a reference-embedding 8 $\times $ interpolating flash (I-Flash) ADC to enhance the conversion speed. Operating the CDAs in a dual-edge manner makes it possible to achieve an 8-bit resolution with only four CDAs and one capacitive digital-to-analog converter (C-DAC), which improves the power and area efficiency as well as the input bandwidth. A prototype ADC implemented in a 28-nm CMOS process occupies a 0.002 mm ² active area. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset calibration is 0.59 and 0.82 LSB, respectively. With a 0.499-GHz input, the measured signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) are 45.5 and 59.4 dB, respectively. The measured effective resolution bandwidth (ERBW) is above 3 GHz. The power consumption at 1-GS/s conversion is 2.55 mW with a supply voltage of 1.1 V, leading to a figure of merit (FoM) of 16.6 fJ/conversion-step.

中文翻译：

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具有28nm CMOS互补动态放大器的8位1-GS / s异步环路展开SAR-Flash ADC

提出了一种具有互补动态放大器（CDA）的8位1-GS / s异步环路展开（LU）逐次逼近寄存器（SAR）-闪存混合模数转换器（ADC）。拟议的ADC是异步LU-SAR ADC和参考嵌入的组合8 $ \次$ 内插闪存（I-Flash）ADC以提高转换速度。以双边缘方式操作CDA使得仅使用四个CDA和一个电容式数模转换器（C-DAC）即可达到8位分辨率，从而提高了功率和面积效率以及输入带宽。采用28 nm CMOS工艺实现的ADC原型占用0.002 mm ²活动区域。失调校准后，测得的差分非线性（DNL）和积分非线性（INL）分别为0.59和0.82 LSB。使用0.499 GHz输入时，测得的信噪比和失真比（SNDR）和无杂散动态范围（SFDR）分别为45.5 dB和59.4 dB。测得的有效分辨率带宽（ERBW）高于3 GHz。1-GS / s转换时的功耗为2.55 mW，电源电压为1.1 V，因此品质因数（FoM）为16.6 fJ /转换步长。