This article presents a fully dynamic ringamp-based pipelined ADC with integrated reference buffer that operates from 1-MS/s to 1-GS/s and maintains a Walden Figure-of-Merit (FoM) of 14 fJ/conversion-step across this range. A “split-reference” regulation technique is introduced, which provides multiple buffered replicas with varying accuracies and output impedances to the core ADC circuitry, relaxing overall buffer design requirements and improving efficiency. The regulator blocks are implemented with fully dynamic discrete-time loops. Furthermore, a technique for background reconstruction of residue amplifier settling behavior is also described. The “scope-on-chip” captures high-resolution transient waveforms using a 1-bit stochastic ADC. It is shown how these waveform data can be used for optimization of ringamp biasing and PVT tracking. The ADC is fabricated in a 16-nm CMOS technology and at 1 GS/s with a Nyquist input achieves 59.5-dB SNDR, 75.9-dB SFDR, and 10.9-mW total power consumption with only 8% consumed by the reference regulation.

中文翻译：

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基于1-MS / s至1-GS / s Ringamp的流水线ADC，具有完整的动态基准电压调节和16nm的随机片上示波器背景监测

本文介绍了一种具有集成参考缓冲器的全动态基于环放大器的流水线ADC，该缓冲器的工作频率范围为1-MS / s至1-GS / s，并且在此过程中，沃尔登品质因数（FoM）保持为14 fJ /转换步长。范围。引入了“分割参考”调节技术，该技术为核心ADC电路提供了具有不同精度和输出阻抗的多个缓冲副本，从而放宽了对缓冲器总体设计的要求，并提高了效率。调节器模块采用全动态离散时间环路实现。此外，还描述了用于残差放大器建立行为的背景重建的技术。“片上示波器”使用1位随机ADC捕获高分辨率瞬态波形。展示了如何将这些波形数据用于优化环形放大器偏置和PVT跟踪。