A single-ended four-level pulse-amplitude modulation (PAM-4) transmitter (TX) for memory interfaces achieves high signal integrity by combining an impedance-matched PAM-4 driver with a three-point ZQ calibration scheme. This improves PAM-4 linearity by allowing the driver to compensate for its impedance variation caused by the change in the drain–source voltage (VDS) to suit the four output levels considering both the TX and the receiver (RX). Resistors and inductors are eliminated from the voltage-mode (VM) driver, reducing the area requirement. The two-tap asymmetric feed-forward equalization (FFE) allocates six different coefficients to each minimum pull-up and pull-down transition, compensating for nonlinear equalization strengths and asymmetric characteristics of the driver. A prototype chip fabricated in the 65-nm CMOS has an area of 0.0333 mm2 and consumes 0.64 pJ/bit. It achieves a data rate of 28 Gb/s/pin with a ratio level separation mismatch (RLM) of 0.993.

中文翻译：

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具有阻抗匹配驱动器和存储器接口三点 ZQ 校准的 0.64-pJ/Bit 28-Gb/s/Pin 高线性度单端 PAM-4 发送器

用于存储器接口的单端四电平脉冲幅度调制 (PAM-4) 发射器 (TX) 通过将阻抗匹配的 PAM-4 驱动器与三点 ZQ 校准方案相结合，实现了高信号完整性。这通过允许驱动器补偿由漏源电压 (VDS) 变化引起的阻抗变化来改善 PAM-4 线性度，以适应考虑 TX 和接收器 (RX) 的四个输出电平。电压模式 (VM) 驱动器中去除了电阻器和电感器，从而减少了面积要求。两抽头非对称前馈均衡 (FFE) 为每个最小上拉和下拉转换分配六个不同的系数，补偿非线性均衡强度和驱动器的非对称特性。在 65 纳米 CMOS 中制造的原型芯片的面积为 0。0333 mm2，消耗 0.64 pJ/bit。它实现了 28 Gb/s/pin 的数据速率，比率电平分离失配 (RLM) 为 0.993。