In this paper, we propose some SQuare-RooT (SQRT) Carry SeLect Adder (CSLA) architectures including a high-speed design, a design with the lowest area compared to previous CSLAs, and two hybrid designs. The first proposed architecture is an optimized design of the Binary to Excess-1 Converter (BEC)-based CSLA by employing a new fast and merged add-one and multiplexing circuit. This architecture in addition to attaining much lower area, delay and energy consumption compared to the BEC CSLA, requires almost the same area compared to the best existing CSLA i.e. IRredundant Carry Generation and Selection scheme (IRCGS CSLA) while providing a higher speed. The second proposed CSLA as the lowest-area design is the area-optimized architecture of IRCGS CSLA that exploits a new logic optimization while maintaining its speed. This scheme makes use of a multiplexer-based logic to reduce the number of gates and to achieve a more compact design. In addition, two hybrid CSLAs are proposed by exploiting the benefits of both proposed CSLA architectures. Experimental results show that the hybrid CSLAs lead to lowest area-delay product and energy-delay product among all the proposed and previous designs in a wide range of 8-bit to 128-bit adder size. In fact, 10–48% reduction in area-delay product and 8–65% reduction in energy-delay product are achieved compared to previous designs. Moreover, the hybrid CSLAs outperform the best existing design with respect to all three parameters of area, delay and energy.

在本文中，我们提出了一些Square-RooT（SQRT）随身加法器（CSLA）架构，包括高速设计，与以前的CSLA相比面积最小的设计以及两种混合设计。首先提出的体系结构是采用新的快速和合并的加法和复用电路对基于二进制至多余1转换器（BEC）的CSLA的优化设计。与BEC CSLA相比，该体系结构不仅面积，延迟和能耗低得多，而且与现有最佳CSLA（即冗余冗余携带生成和选择方案（IRCGS CSLA））相比，所需的面积几乎相同，同时提供了更高的速度。提议的第二个CSLA作为最低区域设计是IRCGS CSLA的区域优化架构，该架构在保持速度的同时利用了新的逻辑优化。该方案利用基于多路复用器的逻辑来减少门数并实现更紧凑的设计。另外，通过利用两种提议的CSLA体系结构的好处，提出了两种混合CSLA。实验结果表明，在所有提议的和先前的设计中，混合CSLA导致在8位至128位加法器大小范围内，面积延迟乘积和能量延迟乘积最低。实际上，与以前的设计相比，面积延迟积减少了10–48％，能量延迟积减少了8–65％。此外，就面积，延迟和能量这三个参数而言，混合式CSLA的性能优于现有的最佳设计。通过利用两种提议的CSLA体系结构的好处，提出了两种混合CSLA。实验结果表明，在所有提议的和先前的设计中，混合CSLA导致在8位至128位加法器大小范围内，面积延迟乘积和能量延迟乘积最低。实际上，与以前的设计相比，面积延迟积减少了10–48％，能量延迟积减少了8–65％。此外，就面积，延迟和能量这三个参数而言，混合式CSLA的性能优于现有的最佳设计。通过利用两种提议的CSLA体系结构的好处，提出了两种混合CSLA。实验结果表明，在所有提议的和先前的设计中，混合CSLA导致在8位至128位加法器大小范围内，面积延迟乘积和能量延迟乘积最低。实际上，与以前的设计相比，面积延迟积减少了10–48％，能量延迟积减少了8–65％。此外，就面积，延迟和能量这三个参数而言，混合式CSLA的性能优于现有的最佳设计。与以前的设计相比，面积延迟积减少了10–48％，能量延迟积减少了8–65％。此外，就面积，延迟和能量这三个参数而言，混合式CSLA的性能优于现有的最佳设计。与以前的设计相比，面积延迟积减少了10–48％，能量延迟积减少了8–65％。此外，就面积，延迟和能量这三个参数而言，混合式CSLA的性能优于现有的最佳设计。