An interesting area of application in wireless data communication is direct-sequence spread spectrum (DSSS). Spread spectrum communication techniques make the signals more robust against interference and jamming. These are based on a concept that narrowband signal is scrambled before transmission in such a way that the signals occupy a much larger part of the radio frequency spectrum. As the digital and the analogue system components are required on the same substrate in today’s mixed-signal chips, the DSSS transmitter system is proposed to be implemented in field-programmable gate array (FPGA)–based platforms and application-specific integrated circuits (ASICs). With a low-power very large-scale integration (VLSI) architecture, sophisticated processing of wide-bandwidth DSSS systems can be exploited in FPGAs/ASICs. In this article, binary pseudo-noise (PN) sequences are generated using a low-power linear feedback shift register (LFSR) in order to spread transmit signals extensively. The proposed low-power design of LFSR and DSSS transmitter with implementation results is illustrated in this paper. Dynamic power dissipation of the proposed DSSS transmitter is reduced up to 15% and 15.6% when compared to the conventional LFSR and the Gold code–based systems respectively. The proposed hardware is implemented in 180-nm technology and operates at 15.36-MHz frequency.

无线序列通信中一个有趣的应用领域是直接序列扩频（DSSS）。扩频通信技术使信号对干扰和干扰更加鲁棒。这些是基于这样的概念，即窄带信号在传输之前被加扰，使得信号占据了射频频谱的很大一部分。由于当今混合信号芯片中的数字和模拟系统组件需要在同一基板上，因此建议在基于现场可编程门阵列（FPGA）的平台和专用集成电路（ASIC）中实现DSSS发射机系统。 ）。借助低功耗超大规模集成（VLSI）架构，可以在FPGA / ASIC中利用宽带DSSS系统的复杂处理能力。在本文中，使用低功率线性反馈移位寄存器（LFSR）生成二进制伪噪声（PN）序列，以便广泛扩展发射信号。本文说明了所提出的LFSR和DSSS发射机的低功耗设计，并给出了实现结果。与传统的LFSR和基于Gold码的系统相比，建议的DSSS发射机的动态功耗分别降低了15％和15.6％。拟议的硬件以180纳米技术实现，并以15.36兆赫的频率运行。与传统的LFSR和基于Gold码的系统相比，建议的DSSS发射机的动态功耗分别降低了15％和15.6％。拟议的硬件以180纳米技术实现，并以15.36兆赫的频率运行。与传统的LFSR和基于Gold码的系统相比，建议的DSSS发射机的动态功耗分别降低了15％和15.6％。拟议的硬件以180纳米技术实现，并以15.36兆赫的频率运行。