This paper presents a CNTFET based ultra-low-power ternary SRAM design which consumes merely 66 nW of power, achieving 84–98% reduction in power consumption as compared to the other CNTFET ternary SRAM designs reported in the literature. The 6-Transistor (6T) Standard Ternary Inverter (STI) cell or the 3T-STI cell form the basic building block of the conventional SRAM cells. These conventional STI designs have an undesirable direct path between V_DD and ground during certain ternary input signals, resulting in higher power consumption. In this paper, a highly power-efficient 4T-STI based Ternary SRAM design is presented, which prevents a direct path between the power supply V_DD and ground in all the possible ternary logic states.

While CNTFET is preferred by many researchers around the world for low-power VLSI applications, CMOS technology is still widely used in the industry because of the availability of advanced CMOS manufacturing units. Therefore, the proposed ultra-low-power ternary SRAM design has been implemented with both 32 nm CNTFET and 45 nm CMOS devices. The performance of both the CNTFET and CMOS based ultra-low-power ternary SRAM circuits have been benchmarked with corresponding conventional SRAM circuits. The overall decrease in Power Delay Product (PDP) is 86–97% in the proposed ultra-low-power ternary 32 nm CNTFET SRAM circuit and 87–99% in the proposed 45 nm CMOS SRAM with respect to corresponding conventional ternary SRAM circuits.

本文介绍了一种基于CNTFET的超低功耗三态SRAM设计，其功耗仅为66 nW，与文献中报道的其他CNTFET三元SRAM设计相比，其功耗降低了84–98％。6晶体管（6T）标准三元反相器（STI）单元或3T-STI单元构成了常规SRAM单元的基本构建块。这些常规的STI设计在某些三态输入信号期间在V _DD与地之间具有不希望有的直接路径，从而导致更高的功耗。本文提出了一种基于高功率效率的基于4T-STI的三态SRAM设计，该设计可防止在所有可能的三态逻辑状态下电源V _DD与地之间的直接路径。

尽管CNTFET在低功耗VLSI应用中被全球许多研究人员所青睐，但由于拥有先进的CMOS制造单元，CMOS技术仍在业界广泛使用。因此，建议的超低功耗三态SRAM设计已在32 nm CNTFET和45 nm CMOS器件中实现。基于CNTFET和CMOS的超低功耗三态SRAM电路的性能已经通过相应的常规SRAM电路进行了基准测试。与相应的传统三元SRAM电路相比，拟议的超低功耗三元32nm CNTFET SRAM电路的功率延迟积（PDP）总体降低了，而拟议的45 nm CMOS SRAM的总延迟降低了87-99％。