This paper presents a dual-modular-redundancy and dual-level error-interception based triple-node-upset (TNU) tolerant latch design (namely DDETT) for safety-critical applications. The DDETT latch comprises two parallel single-node-upset self-recoverable cells to store values and three C-elements to intercept errors. Both of the two cells are constructed from triple mutually-feeding-back 2-input C-elements, and the cells feed two internal C-elements for first-level error-interception. Moreover, the two internal C-elements feed an output-stage C-element for second-level error-interception, making the DDETT latch TNU-tolerant in that it can tolerate any possible TNU. This paper further presents a low-cost version of the DDETT latch, namely LCDDETT. The LCDDETT latch uses two dual-interlocked-storage-cells (DICEs) to store values and uses dual-level error-interception to tolerate any possible TNU with cost-effectiveness. Simulation results not only confirm the TNU-tolerance of the proposed latches but also demonstrate that the delay-power-area products of the DDETT and LCDDETT latches are reduced by approximately 34% and 58%, respectively.

本文针对安全关键型应用提出了一种基于双模块冗余和双级错误拦截的三节点可容错（TNU）容错锁存器设计（即DDETT）。DDETT锁存器包括两个并行的单节点可翻转自恢复单元以存储值，以及三个C元素以拦截错误。这两个单元都由三路相互反馈的2输入C元素构成，并且单元馈送了两个内部C元素用于第一级错误拦截。此外，两个内部C元素为第二级错误拦截提供了输出级C元素，使得DDETT锁存器具有TNU容忍性，因为它可以容忍任何可能的TNU。本文进一步介绍了DDETT锁存器的低成本版本，即LCDDETT。LCDDETT锁存器使用两个双互锁存储单元（DICE）来存储值，并使用双级错误拦截来以成本效益容忍任何可能的TNU。仿真结果不仅证实了所提出锁存器的TNU容限，而且还表明DDETT和LCDDETT锁存器的延迟功率面积乘积分别降低了约34％和58％。