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Design of zero bias power detectors towards power consumption optimization in 5G devices
Microelectronics Journal ( IF 2.2 ) Pub Date : 2021-03-19 , DOI: 10.1016/j.mejo.2021.105035
Issa Alaji , Walid Aouimeur , Haitham Ghanem , Etienne Okada , Sylvie Lépilliet , Daniel Gloria , Guillaume Ducournau , Christophe Gaquière

This paper presents the design and characterization of zero bias power detectors, based on MOSFET transistors, integrated in SiGe 55-nm BiCMOS technology from ST-Microelectronics. The working frequency bands of the circuits are located in the range (38–55) GHz, dedicated to optimize the power consumption in 5G devices. Three NMOS categories available in the technology are used (GP, LP, HPA), the aim is to design several detectors based on different NMOS categories in order to compare their performances. In addition, a detector based on a stack of 6 LP transistors is designed in order to increase the dynamic range. Compared to recent works, the HPA detector exhibits a very good performance with very low noise equivalent power value (NEP) 3.8 pW/Hz and large dynamic range of 67 ​dB. The extracted voltage sensitivity values of these detectors are between (850–1400) V/W showing good agreements with the simulation results.



中文翻译:

面向5G设备功耗优化的零偏置功率检测器设计

本文介绍了基于MOSFET晶体管的零偏置功率检测器的设计和特性,该检测器集成在ST-Microelectronics的SiGe 55-nm BiCMOS技术中。电路的工作频带位于(38–55)GHz范围内,专用于优化5G设备的功耗。使用了该技术中可用的三个NMOS类别(GP,LP,HPA),目的是根据不同的NMOS类别设计几个探测器,以比较它们的性能。此外,设计了一个基于6个LP晶体管堆栈的检测器,以增加动态范围。与最近的工作相比,HPA检测器表现出非常好的性能,而噪声等效功率值(NEP)却很低,仅为3.8 pW /Hž动态范围达67 dB。这些检测器提取的电压灵敏度值在(850-1400)V / W之间,与仿真结果吻合良好。

更新日期:2021-04-02
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