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Improving Write Performance on Cross-Point RRAM Arrays by Leveraging Multidimensional Non-Uniformity of Cell Effective Voltage
IEEE Transactions on Computers ( IF 3.6 ) Pub Date : 2020-04-27 , DOI: 10.1109/tc.2020.2990884
Chengning Wang 1 , Dan Feng 1 , Wei Tong 1 , Jingning Liu 1 , Bing Wu 1 , Wei Zhao 1 , Yang Zhang 1 , Yiran Chen 2
Affiliation  

Resistive cross-point memory arrays can be used to construct high-density storage-class memory. However, coupled IR drop and sneak currents cause multidimensional non-uniformity of cell effective voltage in cross-point arrays. The voltage non-uniformity significantly degrades write performance on cross-point memory if only adopting the worst-case write latency at partial dimensions. Furthermore, the non-uniformity of cell effective voltage in cross-point arrays depends on multidimensional dynamic write operation parameters: row, column as well as layer address, the number of selected cells, and the number of half-selected low-resistance state cells. In this article, we aim to improve the write performance by leveraging multidimensional non-uniformity of cell effective voltage. First, we analyze the impact of multidimensional write parameters on effective voltage and write latency. Then, we design the memory array write scheme that measures the write parameters and sets the write latency accordingly. We further analyze the features and effects of interlayer sneak currents and extend the scheme to 3D cross-point memory. The evaluation shows that the proposed memory array write scheme can reduce the memory access latency by 75.6 and 64.1 percent, and improve the system performance by 4.5 times and 3.4 times on average, compared with the baseline and the state-of-the-art approach, respectively.

中文翻译:

通过利用单元有效电压的多维非均匀性来提高交叉点RRAM阵列的写入性能

电阻性交叉点存储器阵列可用于构造高密度存储类存储器。然而,耦合的IR压降和潜电流在交叉点阵列中引起电池有效电压的多维不均匀性。如果仅在部分尺寸上采用最坏情况下的写入延迟,则电压不均匀性会严重降低交叉点存储器的写入性能。此外,交叉点阵列中单元有效电压的不均匀性取决于多维动态写操作参数:行,列以及层地址,所选单元的数量以及半选低电阻状态单元的数量。在本文中,我们旨在通过利用单元有效电压的多维不均匀性来提高写入性能。第一的,我们分析了多维写入参数对有效电压和写入延迟的影响。然后,我们设计内存阵列写方案,该方案可测量写参数并相应地设置写延迟。我们进一步分析了层间潜电流的特征和影响,并将该方案扩展到3D交叉点存储器。评估显示,与基线和最新方法相比,所提出的存储器阵列写入方案可以将存储器访问延迟减少75.6%和64.1%,并且平均将系统性能提高4.5倍和3.4倍。 , 分别。我们进一步分析了层间潜电流的特征和影响,并将该方案扩展到3D交叉点存储器。评估表明,与基线和最新方法相比,所提出的存储器阵列写入方案可以将存储器访问延迟减少75.6%和64.1%,并且平均将系统性能提高4.5倍和3.4倍。 , 分别。我们进一步分析了层间潜电流的特征和影响,并将该方案扩展到3D交叉点存储器。评估显示,与基线和最新方法相比,所提出的存储器阵列写入方案可以将存储器访问延迟减少75.6%和64.1%,并且平均将系统性能提高4.5倍和3.4倍。 , 分别。
更新日期:2020-04-27
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