This article presents a cascaded gate driver (CGDA) architecture to improve the switching speed of series-connected power devices. The main idea is to propose a new technique to increase dV/dt of the devices when their voltages are already balanced. In complex power converters such as multicell and multilevel topologies, and series-connected power devices, many driver circuits are required and implemented. In such converters, there are several dV/dt sources generated at different floating points associated with the parasitic capacitances of the isolated barriers of the gate drivers (supplies and control signal isolation units), which can amplify the conducted electromagnetic interference (EMI) perturbations, and therefore, the switching speed of the power devices can be affected. This article is focused on the analysis of a new cascaded configuration of gate drivers to increase the switching speed and, consequently, reducing the switching losses of the series-connected transistor topologies. This improvement is achieved by reducing the equivalent parasitic capacitance of the gate driver circuitry considering the gate driver architectures: a new concept of cascaded gate driver is presented. Theoretical and experimental measurements are used to support the cascade gate driver architecture proposed in this article.

中文翻译：

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提高串联功率器件开关速度的级联栅极驱动器架构


本文提出了一种级联栅极驱动器 (CGDA) 架构，用于提高串联功率器件的开关速度。主要思想是提出一种新技术，在电压已经平衡时增加器件的 dV/dt。在复杂的功率转换器（例如多单元和多级拓扑以及串联功率器件）中，需要并实现许多驱动器电路。在此类转换器中，在与栅极驱动器（电源和控制信号隔离单元）的隔离势垒的寄生电容相关的不同浮点处生成多个 dV/dt 源，这些源可以放大传导电磁干扰 (EMI) 扰动，因此，功率器件的开关速度会受到影响。本文重点分析新型栅极驱动器级联配置，以提高开关速度，从而降低串联晶体管拓扑的开关损耗。这种改进是通过考虑栅极驱动器架构降低栅极驱动器电路的等效寄生电容来实现的：提出了级联栅极驱动器的新概念。理论和实验测量用于支持本文提出的级联栅极驱动器架构。