The Fast Fourier Transform (FFT) is the basic building block for DSP applications where high processing speed is the critical requirement. Resource utilization and the number of computational stages in Radix-2 FFT structure implementation can be minimized by improving the performance of utilized multiplier and adder blocks. This work proposes a hardware design of an efficient Radix-2 FFT architecture using optimized multiplier and novel Parallel prefix (PP) adder. The designed FFT architecture results in low power and area with an increase in operation speed in comparison to the existing architectures. Our proposed Radix 2 FFT implementation results in 18.218 ns (6.030 ns logic delay and 12.118 ns router delay) in comparison with 24.003 ns delay for Wallace multiplier using Kogge Stone PP adder (M1P1), 24.162 ns delay for Wallace multiplier using Brent Kung PP adder (M2P2), 24.889 ns delay for Wallace multiplier using Landner Fischer PP adder (M3P3) and 22.827 ns delay for Wallace multiplier using Han Carlson PP adder (M4P4) algorithm. The proposed adder and hence the FFT processor can be used in different applications where high speed, low power, and less area is required. The novel PP architecture results in a 20.19% improvement in comparison with other state-of-art techniques.

快速傅立叶变换（FFT）是DSP应用的基本构建模块，在DSP应用中，高处理速度是至关重要的要求。通过提高利用的乘法器和加法器块的性能，可以最大限度地减少Radix-2 FFT结构实现中的资源利用率和计算级数。这项工作提出了使用优化的乘法器和新颖的并行前缀（PP）加法器的高效Radix-2 FFT架构的硬件设计。与现有架构相比，设计的FFT架构可降低功耗和面积，并提高运算速度。与使用Kogge Stone PP加法器（M1P1）的华莱士乘法器的24.003 ns延迟相比，我们提出的Radix 2 FFT实现产生了18.218 ns（逻辑延迟为6.030 ns，路由器延迟为12.118 ns路由器延迟），相比之下，延迟为24.003 ns。使用Brent Kung PP加法器（M2P2）的Wallace乘法器的延迟为162 ns，使用Landner Fischer PP加法器（M3P3）的Wallace乘法器的延迟为24.889 ns，使用Han Carlson PP加法器（M4P4）的Wallace乘法器的延迟为22.827 ns。所提出的加法器以及FFT处理器可用于需要高速，低功耗和小面积的不同应用中。与其他最先进的技术相比，新颖的PP体系结构可提高20.19％。