In split radix architecture, large sizes Fast Fourier Transforms (FFT) are decomposed into small independent computations to reduce storage burden. Radix-2, 8-point is one the popular choice in split radix for small independent computation. Authors proposes the FFT processor architecture for this small independent computation i.e. radix-2, 8-point FFT. This paper brief architecture comprising Butterfly Unit (BU), register set and controller. The novelty of this architecture is that it replaces the series of Processing Elements (PE) by single BU. BU computes two halves of the computations concurrently. Arithmetic computations are performed in floating point form to overcome the nonlinearities. All computations are controlled by tailored instruction set. All instructions are of same size and have same execution time. Twiddle constants are implicitly available in the instruction. Internal computations are stored in register set to avoid the load and store operations with memory. The mean square error of the computation is reduced by 41.95% and 55.76% in magnitude and phase respectively as compared with computations performed by rounding the twiddle constant. This FFT processor is synthesized, placed and routed for 45 nm technology of nangate open cell library. The BU of this architecture is 18.89% smaller and 5.13% faster as compared with smallest and fastest BU reported previously. The hardware cost metric i.e. D_p mm² ns² mW of proposed processor is 1.37. This cost metric is also 32.51% less as compared with the previous work.

中文翻译：

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Radix-2,8点FFT处理器的ASIC设计

在拆分基数体系结构中，将大尺寸的快速傅立叶变换（FFT）分解为小的独立计算，以减少存储负担。Radix-2（8点）是用于小独立计算的拆分基数中的常用选择之一。作者提出了用于这种小型独立计算的FFT处理器体系结构，即基数2、8点FFT。本文的简要架构包括蝶形单元（BU），寄存器集和控制器。这种架构的新颖之处在于，它用单个BU代替了一系列处理元素（PE）。BU同时计算两半。以浮点形式执行算术计算以克服非线性。所有计算均由量身定制的指令集控制。所有指令大小相同，执行时间相同。旋转常量在指令中隐式可用。内部计算存储在寄存器集中，以避免使用内存进行加载和存储操作。与通过舍入旋转常数进行的计算相比，该计算的均方误差在幅度和相位上分别减少了41.95％和55.76％。该FFT处理器针对Nangate开放单元库的45 nm技术进行了合成，放置和布线。与先前报道的最小和最快的BU相比，此体系结构的BU缩小了18.89％，速度提高了5.13％。硬件成本指标，即D 与四舍五入旋转常数所进行的计算相比，幅度和相位分别为76％。该FFT处理器针对Nangate开放单元库的45 nm技术进行了合成，放置和布线。与先前报道的最小和最快的BU相比，此体系结构的BU缩小了18.89％，速度提高了5.13％。硬件成本指标，即D 与四舍五入旋转常数所进行的计算相比，幅度和相位分别为76％。该FFT处理器针对Nangate开放单元库的45 nm技术进行了合成，放置和布线。与先前报道的最小和最快的BU相比，此体系结构的BU缩小了18.89％，速度提高了5.13％。硬件成本指标，即D建议处理器的_p mm ² ns ² mW为1.37。与以前的工作相比，此成本指标也减少了32.51％。