Purpose

This work focused on a basic building block of an allocation unit that carries out the critical job of deciding between the conflicting requests, i.e. an arbiter unit. The purpose of this work is to implement an improved hybrid arbiter while harnessing the basic advantages of a matrix arbiter.

Design/methodology/approach

The basic approach of the design methodology involves the extraction of traffic information from buffer signals of each port. As the traffic arrives in the buffer of respective ports, information from these buffers acts as a source of differentiation between the ports receiving low traffic rates and ports receiving high traffic rates. A logic circuit is devised that enables an arbiter to dynamically assign priorities to different ports based on the information from buffers. For implementation and verification of the proposed design, a two-stage approach was used. Stage I comprises comparing the proposed arbiter with other arbiters in the literature using Vivado integrated design environment platform. Stage II demonstrates the implementation of the proposed design in Cadence design environment for application-specific integrated chip level implementation. By using such a strategy, this study aims to have a special focus on the feasibility of the design for very large-scale integration implementation.

Findings

According to the simulation results, the proposed hybrid arbiter maintains the advantage of a basic matrix arbiter and also possesses the additional feature of fault-tolerant traffic awareness. These features for a hybrid arbiter are achieved with a 19% increase in throughput, a 1.5% decrease in delay and a 19% area increase in comparison to a conventional matrix arbiter.

Originality/value

This paper proposes a traffic-aware mechanism that increases the throughput of an arbiter unit with some area trade-off. The key feature of this hybrid arbiter is that it can assign priorities to the requesting ports based upon the real-time traffic requirements of each port. As a result of this, the arbiter is dynamically able to make arbitration decisions. Now because buffer information is valuable in winning the priority, the presence of a fault-tolerant policy ensures that none of the priority is assigned falsely to a requesting port. By this, wastage of arbitration cycles is avoided and an increase in throughput is also achieved.

中文翻译：

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用于实时流量感知调度的自适应混合仲裁器设计

目的

这项工作的重点是分配单元的基本构建块，该单元执行在冲突请求之间做出决定的关键工作，即仲裁器单元。这项工作的目的是在利用矩阵仲裁器的基本优势的同时实现改进的混合仲裁器。

设计/方法/方法

设计方法的基本方法涉及从每个端口的缓冲信号中提取交通信息。当流量到达各个端口的缓冲区时，来自这些缓冲区的信息充当接收低流量速率的端口和接收高流量速率的端口之间的区别源。设计了一种逻辑电路，使仲裁器能够根据来自缓冲区的信息动态地将优先级分配给不同的端口。为了实施和验证所提出的设计，使用了两阶段方法。第一阶段包括使用 Vivado 集成设计环境平台将提议的仲裁器与文献中的其他仲裁器进行比较。第二阶段演示了在 Cadence 设计环境中针对特定应用的集成芯片级实现所提出的设计的实现。通过使用这种策略，本研究旨在特别关注超大规模集成实施设计的可行性。

发现

根据仿真结果，所提出的混合仲裁器保持了基本矩阵仲裁器的优点，还具有容错流量感知的附加特性。与传统矩阵仲裁器相比，混合仲裁器的这些特性通过增加 19% 的吞吐量、减少 1.5% 的延迟和增加 19% 的面积来实现。

原创性/价值

本文提出了一种流量感知机制，该机制通过一些区域权衡来增加仲裁器单元的吞吐量。这种混合仲裁器的关键特性是它可以根据每个端口的实时流量需求为请求端口分配优先级。因此，仲裁器能够动态地做出仲裁决定。现在，由于缓冲区信息对于赢得优先级很有价值，因此容错策略的存在可确保没有任何优先级被错误地分配给请求端口。这样，避免了仲裁周期的浪费并且还实现了吞吐量的增加。