This article characterizes three parasitic capacitances in copper-foiled medium-voltage inductors. It is found that the conventional modeling method overlooks the effect of the fringe field, which leads to inaccurate modeling of parasitic capacitances in copper-foiled inductors. To address this problem, the parasitic capacitances contributed by the fringe electrical field is identified first, and a physics-based analytical modeling method for the parasitic capacitances contributed by the fringe electrical field is proposed, which avoids using any empirical equations. The total parasitic capacitances are then derived for three different cases with three different core potentials, from which a three-terminal equivalent circuit is derived, and thus, the parasitic capacitances in copper-foiled inductors are explicitly identified. The calculated results show a close agreement with the measured capacitance by using an impedance analyzer. Two recommendations for reducing the parasitic capacitances in copper-foiled inductors are given in this article.

中文翻译：

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考虑边缘电场的铜箔中压滤波电感的寄生电容建模

本文描述了铜箔中压电感器中的三个寄生电容。发现传统的建模方法忽略了边缘场的影响，这导致铜箔电感器中寄生电容的建模不准确。为了解决这个问题，首先要确定由边缘电场贡献的寄生电容，并提出了一种基于物理学的由边缘电场贡献的寄生电容的解析建模方法，该方法避免了使用任何经验方程式。然后，针对具有三种不同铁芯电势的三种不同情况得出总寄生电容，从中得出三端等效电路，从而明确确定了铜箔电感器中的寄生电容。通过使用阻抗分析仪，计算结果表明与测得的电容非常吻合。本文提出了两种减少铜箔电感中寄生电容的建议。