In this study, an analog circuit design instead of using a software is utilized to remove Salt and Pepper (S&P) noise in image. For this purpose, a digital image filtering method which is called median filter is carried out. In median filter method, a current-mode nine-input one-output circuit architecture is preferred since 3 × 3 filtering mask is employed. Median filter circuit is based on a modified bitonic sort network and consists of 26 max/min selector circuits. A current-mode two-input two-output circuit is designed as a max/min selector and there is no biasing current source in the max/min selector structure. In analysis part, two 150 × 150 images with different amount of S&P noise are used and the noise in image is successfully reduced with the help of the proposed circuit design. The performance of the suggested median filter is also verified through the quality measurement parameters such as Structural Similarity Index Metric, Mean Squared Error, Mean Absolute Error and Peak Signal to Noise Ratio. TSMC CMOS 0.18 µm process model is utilized to simulate the introduced median filter circuit.

在这项研究中，模拟电路设计代替了使用软件来消除图像中的椒盐（S＆P）噪声。为此目的，执行了一种被称为中值滤波器的数字图像滤波方法。在中值滤波方法中，由于采用了3×3滤波模板，因此最好采用电流模式九输入一输出电路架构。中值滤波电路基于改进的双子分类网络，由26个最大/最小选择器电路组成。电流模式两输入两输出电路被设计为最大/最小选择器，并且最大/最小选择器结构中没有偏置电流源。在分析部分中，使用了两个具有不同S＆P噪声量的150×150图像，并借助所提出的电路设计成功降低了图像中的噪声。建议的中值滤波器的性能也可以通过质量测量参数来验证，例如结构相似性指标度量，均方误差，均值绝对误差和峰值信噪比。台积电CMOS 0.18 µm工艺模型用于模拟引入的中值滤波电路。