As new applications impose jitter values in the range of a few tens of femtoseconds, the design of phase-locked loops faces daunting challenges. This paper derives basic relations between the tolerable jitter and the power consumption, predicting severe issues as jitters below 10 fs are sought. The results are also applied to the sampling clocks in analog-to-digital converters and suggest that clock generation may consume a greater power than the converter itself.

中文翻译：

---

PLL 中的抖动功率权衡


随着新应用施加几十飞秒范围内的抖动值，锁相环的设计面临着严峻的挑战。本文推导了可容忍抖动与功耗之间的基本关系，预测了当抖动低于 10 fs 时会出现严重问题。结果还应用于模数转换器中的采样时钟，并表明时钟生成可能比转换器本身消耗更大的功率。