This article investigates the effects of different gate coupling voltage and gate voltage duration on electro-static discharge (ESD) performance of several NMOS-based power rail protection devices. Through simulation and transmission line pulse (TLP) test, it is found that there are two modes in the conduction process of the main clamping NMOS: channel conduction state and parasitic NPN conduction state. Different gate voltage and duration bring the two conduction states different proportions in the whole working process, which give the device very different robustness. The results show that under the condition of small gate voltage and long duration and the condition of large gate voltage and short duration, the device can achieve optimal performance because the trigger voltage can be reduced, and the parasitic NPN can be turned on in time to release most of the current.

本文研究了不同的栅极耦合电压和栅极电压持续时间对几种基于NMOS的电源轨保护器件的静电放电（ESD）性能的影响。通过仿真和传输线脉冲（TLP）测试，发现主钳位NMOS的导通过程有两种模式：沟道导通状态和寄生NPN导通状态。不同的栅极电压和持续时间会在整个工作过程中使两种导通状态比例不同，从而使器件的鲁棒性大大不同。结果表明，在栅极电压小且持续时间长的条件下以及栅极电压大且持续时间短的条件下，由于可以降低触发电压，因此该器件可以达到最佳性能，