Directed acyclic graphs or Bayesian networks that are popular in many AI-related sectors for probabilistic inference and causal reasoning can be mapped to probabilistic circuits built out of probabilistic bits (p-bits), analogous to binary stochastic neurons of stochastic artificial neural networks. In order to satisfy standard statistical results, individual p-bits not only need to be updated sequentially but also in order from the parent to the child nodes, necessitating the use of sequencers in software implementations. In this article, we first use SPICE simulations to show that an autonomous hardware Bayesian network can operate correctly without any clocks or sequencers, but only if the individual p-bits are appropriately designed. We then present a simple behavioral model of the autonomous hardware illustrating the essential characteristics needed for correct sequencer-free operation. This model is also benchmarked against SPICE simulations and can be used to simulate large-scale networks. Our results could be useful in the design of hardware accelerators that use energy-efficient building blocks suited for low-level implementations of Bayesian networks. The autonomous massively parallel operation of our proposed stochastic hardware has biological relevance since neural dynamics in brain is also stochastic and autonomous by nature.

在许多人工智能相关领域中流行的用于概率推理和因果推理的有向无环图或贝叶斯网络可以映射到由概率位（p 位）构建的概率电路，类似于随机人工神经网络的二进制随机神经元。为了满足标准的统计结果，各个p位不仅需要顺序更新，而且还需要按照从父节点到子节点的顺序更新，因此需要在软件实现中使用定序器。在本文中，我们首先使用 SPICE 模拟来证明自主硬件贝叶斯网络可以在没有任何时钟或定序器的情况下正确运行，但前提是各个 p 位设计得当。然后，我们提出了一个简单的自主硬件行为模型，说明了正确的无定序器操作所需的基本特征。该模型还以 SPICE 仿真为基准，可用于仿真大规模网络。我们的结果可用于硬件加速器的设计，这些硬件加速器使用适合贝叶斯网络低级实现的节能构建块。我们提出的随机硬件的自主大规模并行操作具有生物学相关性，因为大脑中的神经动力学本质上也是随机和自主的。