This paper proposes a Silicon Carbide (SiC) based planar junctionless transistor (JLT), designed and simulated for low to medium power electronic applications, with a calibrated deck of SiC parameters. The simple structure of this device avoids the fabrication complexity associated with intricate junction geometries of vertical power devices and growth challenges of lateral heterostructure ones. Because of the wide bandgap (WBG) of SiC, the device exhibits a breakdown voltage of 100 V at channel length of 0.1 μm, which may be enhanced, at the cost of operating speed, by increasing the channel length. Compared to commercial enhancement-mode GaN (e-GaN) devices with similar breakdown voltage specification, the proposed device offers lower specific on-resistance (R _on,sp ), and a significant reduction in capacitance due to its naturally self-aligned structure, leading to higher operating speed concluded from the mixed-mode simulations.

本文提出了一种基于碳化硅（SiC）的平面无结晶体管（JLT），它针对SiC参数经过校准的中低功率电子应用进行了设计和仿真。该器件的简单结构避免了与垂直功率器件的复杂结几何形状相关的制造复杂性，也避免了横向异质结构器件的增长挑战。因为宽带隙的SiC（WBG）的，该装置具有以0.1信道长度100伏的击穿电压μ米，其可以提高，在运行速度，通过增加沟道长度的成本。与具有类似击穿电压规格的商用增强型GaN（e-GaN）器件相比，该器件的导通电阻更低（R _{on， sp} ），并且由于其自然的自对准结构而大大降低了电容，从而导致混合模式仿真得出更高的工作速度。