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Stress analysis and structural optimization of 3-D IC package based on the Taguchi method
Soldering & Surface Mount Technology ( IF 1.7 ) Pub Date : 2019-07-29 , DOI: 10.1108/ssmt-04-2019-0016
Ming-Yue Xiong , Liang Zhang , Peng He , Wei-Min Long

The transistor circuit based on Moore's Law is approaching the performance limit. The three-dimensional integrated circuit (3-D IC) is an important way to implement More than Moore. The main problems in the development of 3-D IC are Joule heating and stress. The stresses and strains generated in 3-D ICs will affect the performance of electronic products, leading to various reliability issues. The intermetallic compound (IMC) joint materials and structures are the main factors affecting 3-D IC stress. The purpose of this paper is to optimize the design of the 3-D IC.,To optimize the design of 3-D IC, the numerical model of 3-D IC was established. The Taguchi experiment was designed to simulate the influence of IMC joint material, solder joint array and package size on 3-D IC stress.,The simulation results show that the solder joint array and IMC joint materials have great influence on the equivalent stress. Compared with the original design, the von Mises stress of the optimal design was reduced by 69.96 per cent, the signal-to-noise ratio (S/N) was increased by 10.46 dB and the fatigue life of the Sn-3.9Ag-0.6Cu solder joint was increased from 415 to 533 cycles, indicating that the reliability of the 3-D IC has been significantly improved.,It is necessary to study the material properties of the bonded structure since 3-D IC is a new packaging structure. Currently, there is no relevant research on the optimization design of solder joint array in 3-D IC. Therefore, the IMC joint material, the solder joint array, the chip thickness and the substrate thickness are selected as the control factors to analyze the influence of various factors on the 3-D IC stress and design. The orthogonal experiment is used to optimize the structure of the 3-D IC.

中文翻译:

基于田口法的3D IC封装应力分析与结构优化

基于摩尔定律的晶体管电路正在接近性能极限。三维集成电路(3-D IC)是实现More than Moore的重要途径。3-D IC开发的主要问题是焦耳热和应力。3-D IC 中产生的应力和应变会影响电子产品的性能,从而导致各种可靠性问题。金属间化合物 (IMC) 接头材料和结构是影响 3-D IC 应力的主要因素。本文的目的是优化3-D IC的设计。为了优化3-D IC的设计,建立了3-D IC的数值模型。田口实验旨在模拟 IMC 接头材料、焊点阵列和封装尺寸对 3-D IC 应力的影响。仿真结果表明,焊点阵列和IMC接头材料对等效应力影响较大。与原始设计相比,优化设计的von Mises应力降低了69.96%,信噪比(S/N)提高了10.46 dB,Sn-3.9Ag-0.6的疲劳寿命Cu焊点从415个周期增加到533个周期,表明3-D IC的可靠性得到了显着提高。由于3-D IC是一种新型封装结构,因此有必要研究键合结构的材料特性。目前,对于3-D IC中焊点阵列的优化设计还没有相关的研究。因此,IMC接头材料,焊点阵列,选取芯片厚度和基板厚度作为控制因素,分析各因素对3-D IC应力和设计的影响。正交实验用于优化3-D IC的结构。
更新日期:2019-07-29
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