Purpose

There are many types of the ADCs implemented in the mobile and wireless devices. Most of these devices are battery operated and operational at low input voltage. SAR ADC is popular for its low power operations and simple architecture. Scientists are still working to make its working faster under the same low power area. There are many SAR-ADC implemented in the past two decades, but still, there is a big room for dual SAR-ADC.

Design/methodology/approach

The authors are presenting a dual SAR-ADC with a smaller number of components and blocks. The proposed ultra-low-power circuit of the SAR-ADC consists of four major blocks, which include Bee-bootstrap, Spider-Latch dual comparator, dual SAR-logic and dual digital to analog converter. The authors have used the 90-nm CMOS library for the construction of the design.

Findings

The power breaks down of the comparator are dramatically improved from 0.006 to 0.003 uW. The ultimate design has 5 MHz operating frequency with 25 KS/s sampling frequency. The supply voltage is 1.2 V with 35.724 uW power consumption. Signal-to-noise and distortion ratio and spurious-free dynamic range are 65 and 84 dB, respectively. The Walden's figure of merits calculated 7.08 fj/step.

Originality/value

The authors are proposing two-in-one circuit for SAR-ADC named as “dual SAR-ADC”, which obeys the basic equation of duality, derived and proved under the heading of proposed solution. It shows a clear difference between the performance of two circuit-based ADC and one dual circuit ADC. The number of components is reduced by sharing the work load of some key components.

中文翻译：

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用于超低功耗 SAR-ADC 的蜜蜂自举和蜘蛛锁比较器的仿生电路

目的

在移动和无线设备中实现了多种类型的 ADC。这些设备中的大多数都是电池供电的，并且在低输入电压下运行。SAR ADC 因其低功耗操作和简单的架构而广受欢迎。科学家们仍在努力使其在相同的低功率区域下工作得更快。在过去的二十年中实现了许多 SAR-ADC，但双 SAR-ADC 仍有很大的空间。

设计/方法/方法

作者正在展示一种具有较少组件和模块的双 SAR-ADC。所提出的 SAR-ADC 超低功耗电路由四个主要模块组成，包括 Bee-bootstrap、Spider-Latch 双比较器、双 SAR 逻辑和双数模转换器。作者使用 90-nm CMOS 库来构建设计。

发现

比较器的击穿功率从 0.006 uW 显着提高到 0.003 uW。终极设计具有 5 MHz 的工作频率和 25 KS/s 的采样频率。电源电压为 1.2 V，功耗为 35.724 uW。信噪比和失真比以及无杂散动态范围分别为 65 和 84 dB。Walden 的品质因数计算为 7.08 fj/step。

原创性/价值

作者提出了用于 SAR-ADC 的二合一电路，命名为“双 SAR-ADC”，它遵循对偶的基本方程，在所提出的解决方案的标题下推导和证明。它显示了两个基于电路的 ADC 和一个双电路 ADC 的性能之间的明显差异。通过分担一些关键组件的工作量来减少组件的数量。