In this paper, we have proposed a simple and zero-cost technique to improve ON-state and reliability performance of LDMOS transistors. We introduced doping gradient in the channel by optimizing position of the P-Well mask during test structure design/layout. Through proper device design, fabrication and measurement on different test structures, we have shown that the graded channel significantly improves the drive capability (upto ~30%), analog FoMs and hot-carrier reliability of LDMOS transistors without any penalty on the OFF-state performance. The performance improvement is independent of drift region design (breakdown voltage). The device physics behind different observations is also discussed with detailed TCAD simulations.

中文翻译：

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零成本技术可改善功率LDMOS晶体管的导通状态性能和可靠性

在本文中，我们提出了一种简单且零成本的技术来改善LDMOS晶体管的导通状态和可靠性。通过在测试结构设计/布局过程中优化P-Well掩模的位置，我们在沟道中引入了掺杂梯度。通过在不同的测试结构上进行适当的器件设计，制造和测量，我们已经证明，渐变通道可显着提高LDMOS晶体管的驱动能力（高达〜30％），模拟FoM和热载流子可靠性，而不会对OFF状态造成任何影响表现。性能改善与漂移区设计（击穿电压）无关。还通过详细的TCAD仿真讨论了不同观察结果背后的设备物理原理。