This paper proposes a circuit-level model of an inverter-based switched-capacitor (SC) integrator involved in a previously published incremental sigma-delta analog-to-digital converter (I\(\Sigma {\Delta }\) ADC) to explain the ADC resolution degradation observed in the post-layout simulation. A fine analysis of post-layout signals led to a new model of the integrator with parasitic capacitors. Then the model has been included in the I\(\Sigma {\Delta }\) ADC model, which has been simulated with Matlab. To get detailed results and be able to handle comparisons, various calibration techniques have been applied to the I\(\Sigma {\Delta }\) ADC outputs coming from post-layout simulation and from the new model so that a better resolution is achieved. The results show a good likeness of the error shapes and magnitudes for the new model compared to post-layout simulations. We deduce that the proposed model is a good representation of the degradation phenomena, this with a high level of confidence.

本文提出了一个基于逆变器的开关电容器（SC）积分器的电路级模型，该模型涉及先前发布的增量sigma-delta模数转换器（I \（\ Sigma {\ Delta} \） ADC）解释在布局后仿真中观察到的ADC分辨率下降。对布局后信号的精细分析导致了带有寄生电容器的积分器的新模型。然后，该模型已包含在I \（\ Sigma {\ Delta} \） ADC模型中，该模型已使用Matlab进行了仿真。为了获得详细的结果并能够进行比较，已将各种校准技术应用于I \（\ Sigma {\ Delta} \）ADC输出来自布局后仿真和新模型，因此可获得更好的分辨率。结果表明，与布局后仿真相比，新模型的误差形状和幅度具有良好的相似性。我们推断，所提出的模型可以很好地表示退化现象，并且具有很高的置信度。