In this paper, an inverter-based true time delay (TTD) cell for timed array receivers is proposed. The proposed TTD cell is designed in TSMC 0.18 µm CMOS technology for multi-GHz operations. The delay cell is made from an all-pass filter by Padé approximation. The first-order all-pass filter is built by combining a constant gain stage and a low pass stage based on the approximation. The constant gain stage consists of two NMOS transistors. The low pass stage is created with an inverter cell, cascaded with a PMOS transistor. Active true time delay cells are used in delay lines (commonly in cascaded topology) to develop a timed array system. Because of that, size of the TTD cell is critical and is an important design factor. So in this paper, an inductorless inverter-based wideband TTD cell is proposed. The wideband input impedance matching is achieved without bulky inductors using the resistive feedback technique in the inverter cell. More than wideband input impedance matching, flat gain, and flat delay response for the TTD cell are obtained with this technique. With the inverter-based input and complementary output structure, the TTD cell is a self-biased circuit. So, additional bias circuit is not needed. The proposed TTD cell consumes 8.7 mW from a 1.8 V supply. The achieved wideband delay is 10.6pS. Only 3% delay deviation over the 1–5 GHz band is observed, and this shows the excellent quality of the provided delay. The insertion loss is − 3.9 dB and is tolerable for a TTD cell. The input and output wideband impedance matching is ensured, and the S₁₁ and S₂₂ parameters are lower than -14.7 dB and − 10.9 dB, respectively. At last, the proposed TTD cell shows good linear performance, and IIP3 is around + 11.7 dBm.

本文提出了一种用于定时阵列接收机的基于逆变器的真实时间延迟（TTD）单元。拟议的TTD单元采用TSMC 0.18 µm CMOS技术设计，可用于多GHz操作。延迟单元由Padé近似的全通滤波器制成。一阶全通滤波器是通过基于近似值组合恒定增益级和低通级而构建的。恒定增益级由两个NMOS晶体管组成。低通级由一个反相器单元和一个PMOS晶体管级联而成。有源真实时间延迟单元用于延迟线（通常在级联拓扑中）以开发定时阵列系统。因此，TTD单元的大小至关重要，并且是重要的设计因素。因此，本文提出了一种基于无电感器的基于逆变器的宽带TTD单元。在逆变器单元中使用电阻反馈技术，无需笨重的电感器即可实现宽带输入阻抗匹配。使用该技术，可以获得更多的TTD单元宽带输入阻抗匹配，平坦增益和平坦延迟响应。凭借基于逆变器的输入和互补输出结构，TTD单元是一个自偏置电路。因此，不需要额外的偏置电路。拟议的TTD电池在1.8 V电源下的功耗为8​​.7 mW。达到的宽带延迟为10.6pS。在1–5 GHz频带上仅观察到3％的延迟偏差，这表明所提供的延迟具有出色的质量。插入损耗为-3.9 dB，对于TTD单元是可以容忍的。确保输入和输出宽带阻抗匹配，并且S 利用该技术，可以获得更多的TTD单元宽带输入阻抗匹配，平坦增益和平坦延迟响应。凭借基于逆变器的输入和互补输出结构，TTD单元是一个自偏置电路。因此，不需要额外的偏置电路。拟议的TTD电池在1.8 V电源下的功耗为8​​.7 mW。达到的宽带延迟为10.6pS。在1–5 GHz频带上仅观察到3％的延迟偏差，这表明所提供的延迟具有出色的质量。插入损耗为-3.9 dB，对于TTD单元是可以容忍的。确保输入和输出宽带阻抗匹配，并且S 使用该技术，可以获得更多的TTD单元宽带输入阻抗匹配，平坦增益和平坦延迟响应。凭借基于逆变器的输入和互补输出结构，TTD单元是一个自偏置电路。因此，不需要额外的偏置电路。拟议的TTD电池在1.8 V电源下的功耗为8​​.7 mW。达到的宽带延迟为10.6pS。在1–5 GHz频带上仅观察到3％的延迟偏差，这表明所提供的延迟具有出色的质量。插入损耗为-3.9 dB，对于TTD单元是可以容忍的。确保输入和输出宽带阻抗匹配，并且S 因此，不需要额外的偏置电路。拟议的TTD电池在1.8 V电源下的功耗为8​​.7 mW。达到的宽带延迟为10.6pS。在1–5 GHz频带上仅观察到3％的延迟偏差，这表明所提供的延迟具有出色的质量。插入损耗为-3.9 dB，对于TTD单元是可以容忍的。确保输入和输出宽带阻抗匹配，并且S 因此，不需要额外的偏置电路。拟议的TTD电池在1.8 V电源下的功耗为8​​.7 mW。达到的宽带延迟为10.6pS。在1–5 GHz频带上仅观察到3％的延迟偏差，这表明所提供的延迟具有出色的质量。插入损耗为-3.9 dB，对于TTD单元是可以容忍的。确保输入和输出宽带阻抗匹配，并且S₁₁和S ₂₂参数分别低于-14.7 dB和− 10.9 dB。最后，提出的TTD单元显示出良好的线性性能，IIP3约为+ 11.7 dBm。