Experimental results obtained for 2.3 kV SiC planar-gate power JBSFETs with different cell topologies are analyzed in this article using analytical models and numerical simulations. All the accumulation-channel devices were simultaneously manufactured in a 6-inch commercial foundry with channel length of 0.5 μm and gate oxide thickness of 55 nm. The Schottky contact width was chosen to achieve an on-state voltage drop of below 2.8 V in the 3rd quadrant for the integrated JBS diodes. Lower specific on-resistance of the Hexagonal and higher values for the Octagonal cell topologies compared with the conventional Linear cell design were experimentally observed. New analytical models developed for the various cell topologies reveal that these differences arise from changes in the relative contributions from the N+ source contact, channel, and accumulation region resistances. The analysis reported in this article provides new insight on the importance of the accumulation layer resistance to the Octagonal cell topology. Numerical simulation reveal that the measured leakage current behavior correlates with the electric field observed at the Schottky contact within the 2.3 kV JBSFET cell structures. The leakage current begins to rise rapidly when the electric field exceeds 1.5 MV/cm due to Schottky barrier lowering and enhanced tunneling. The reverse transfer capacitance and gate charge were found to correlate with the JFET region density within the different cell topologies. The measured on-state voltage drop in the third quadrant was found to correlate with the JBS diode density in the cell topologies. A new high-frequency figure-of-merit [Vf3Q* Qgd,sp] is proposed for SiC JBSFETs. The Octagonal cell designs are found to be the most suitable for high frequency applications of 2.3 kV JBSFETs based on the HF-FOMs [Ron* Qgd] and [Vf3Q* Qgd,sp].

中文翻译：

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2.3 kV 4H-SiC 平面栅极累积通道功率 JBSFET：实验数据分析


本文使用分析模型和数值模拟对具有不同单元拓扑的 2.3 kV SiC 平面栅极功率 JBSFET 获得的实验结果进行了分析。所有累积沟道器件均在 6 英寸商业代工厂中同时制造，沟道长度为 0.5 μm，栅极氧化物厚度为 55 nm。选择肖特基接触宽度是为了在集成 JBS 二极管的第三象限中实现低于 2.8 V 的通态压降。实验观察到，与传统的线性电池设计相比，六边形电池的比导通电阻较低，八边形电池拓扑的比导通电阻较高。针对各种电池拓扑开发的新分析模型表明，这些差异是由 N+ 源极接触、沟道和积累区电阻的相对贡献的变化引起的。本文报告的分析提供了关于累积层电阻对八边形电池拓扑的重要性的新见解。数值模拟表明，测得的漏电流行为与 2.3 kV JBSFET 单元结构内肖特基接触处观察到的电场相关。当电场超过 1.5 MV/cm 时，由于肖特基势垒降低和隧道效应增强，漏电流开始迅速上升。研究发现反向传输电容和栅极电荷与不同单元拓扑中的 JFET 区域密度相关。发现第三象限中测得的通态压降与单元拓扑中的 JBS 二极管密度相关。为 SiC JBSFET 提出了一种新的高频品质因数 [Vf3Q* Qgd,sp]。 八边形单元设计被发现最适合基于 HF-FOM [Ron* Qgd] 和 [Vf3Q* Qgd,sp] 的 2.3 kV JBSFET 的高频应用。