Ising machines are hardware devices that can solve ground-state search problems of Ising spin models and could be of use in solving various practical combinatorial optimization problems. However, large-scale systems have to be implemented by partitioning into subsystems that are hard to synchronize and where communication between them is difficult. Here, we report a scale-out architecture for Ising machines that provides enlarged machine sizes and enhanced processing speeds by using multiple connected chips. The architecture is based on the partitioned version of a quantum-inspired algorithm called simulated bifurcation. To maintain time consistency between multiple chips and a sufficiently small stall rate for every time-evolution step in simulated bifurcation, the architecture relies on an autonomous synchronization mechanism that is implemented in the information exchange processes between neighbouring chips and leads to scalability of computational throughput. Our eight-FPGA (field-programmable gate array) simulated bifurcation machine can obtain high-quality solutions to a 16,384-node MAX-CUT problem in 1.2 ms, which is 828 times faster than an optimized implementation of simulated annealing.

伊辛机是可以解决伊辛自旋模型的基态搜索问题的硬件设备，可用于解决各种实际的组合优化问题。然而，大规模系统必须通过划分为难以同步且它们之间难以通信的子系统来实现。在这里，我们报告了 Ising 机器的横向扩展架构，该架构通过使用多个连接的芯片来提供更大的机器尺寸和更高的处理速度。该架构基于称为模拟分岔的量子启发算法的分区版本。为了保持多个芯片之间的时间一致性和模拟分叉中每个时间演化步骤的足够小的失速率，该架构依赖于在相邻芯片之间的信息交换过程中实现的自主同步机制，并导致计算吞吐量的可扩展性。我们的 8 个 FPGA（现场可编程门阵列）模拟分岔机可以在 1.2 ms 内获得 16,384 个节点的 MAX-CUT 问题的高质量解决方案，比模拟退火的优化实现快 828 倍。