With the aggressive scaling of the transistor, Negative Bias Temperature Instability (NBTI) has become the most dominant aging effect which causes the device parameter to degrade over its lifetime. This device parameter degradation of logic gates in nanometer technology is a major concern for the reliability of the digital circuit. It becomes even more critical when it comes to power gating structure, as small NBTI effect on PMOS sleep transistor used in header-based power gating structure would seriously affect the reliability, performance of the whole logic circuit. The conventional method of mitigating the NBTI effect is to oversize the sleep transistor, but it also gives rise to leakage overhead. In this work, a novel NBTI aware power gating architecture is presented to improve the lifetime of the circuit. Here, sleep transistors (STs) are switched ON/OFF periodically and a greater number of STs are turned ON, when NBTI related degradation reaches to its threshold value so that STs get more time to anneal NBTI degradation and improve its lifetime. Simulation result on ISCAS’85 benchmark circuits shows for 40% sleep signal, an average of 51.2% and 14% lifetime improvement with respect to the conventional over-sizing (OS) technique and normal stress probability control method, respectively with some power and area overhead.

中文翻译：

---

NBTI 感知电源门控设计，对睡眠晶体管进行动态变化应力概率控制

随着晶体管的大规模扩展，负偏置温度不稳定性 (NBTI) 已成为最主要的老化效应，它会导致器件参数在其使用寿命期间退化。纳米技术中逻辑门的这种器件参数退化是数字电路可靠性的主要问题。当涉及到电源门控结构时，它变得更加关键，因为基于接头的电源门控结构中使用的 PMOS 休眠晶体管的 NBTI 影响很小，会严重影响整个逻辑电路的可靠性和性能。减轻 NBTI 效应的传统方法是加大休眠晶体管的尺寸，但这也会增加泄漏开销。在这项工作中，提出了一种新颖的 NBTI 感知电源门控架构，以提高电路的使用寿命。这里，当与 NBTI 相关的退化达到其阈值时，睡眠晶体管 (ST) 会定期打开/关闭，并且更多的 ST 会打开，以便 ST 有更多时间对 NBTI 退化进行退火并提高其寿命。ISCAS'85 基准电路的仿真结果显示，对于 40% 的睡眠信号，相对于传统的超尺寸 (OS) 技术和正常应力概率控制方法，平均寿命提高了 51.2% 和 14%，分别具有一些功率和面积高架。