Performance increase with general-purpose processors has come to a halt. We can no longer depend on Moore's Law to increase computing performance. The only way to achieve higher performance or lower energy consumption is by building domain-specific hardware accelerators. To efficiently design and verify those domain-specific accelerators, we need agile hardware development. One of the main obstacles when proposing such a modern method is the lack of modern tools to attack it. To be able to verify a design in such a time-constrained development method, one needs to have efficient tools both for design and verification. This paper thus proposes ChiselVerify, an open-source tool for verifying circuits described in any Hardware Description Language. It builds on top of the Chisel hardware construction language and uses Scala to drive the verification using a testing strategy inspired by the Universal Verification Methodology (UVM) and adapted for designs described in Chisel. ChiselVerify is created based on three key ideas. First, our solution highly increases the productivity of the verification engineer, by allowing hardware testing to be done in a modern high-level programming environment. Second, the framework functions with any hardware description language thanks to the flexibility of Chisel blackboxes. Finally, the solution is well integrated into the existing Chisel universe, making it an extension of currently existing testing libraries. We implement ChiselVerify in a way inspired by the functionalities found in SystemVerilog. This allows one to use functional coverage, constrained-random verification, bus functional models, transaction-level modeling and much more during the verification process of a design in a contemporary high-level programming ecosystem.

中文翻译：

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使用Chisel和Scala进行开源验证

通用处理器的性能提升已停止。我们不再能够依靠摩尔定律来提高计算性能。实现更高性能或更低能耗的唯一方法是构建特定于域的硬件加速器。为了有效地设计和验证那些特定于域的加速器，我们需要敏捷的硬件开发。提出这种现代方法的主要障碍之一是缺乏攻击它的现代工具。为了能够以这种受时间限制的开发方法来验证设计，人们需要同时具有用于设计和验证的有效工具。因此，本文提出了ChiselVerify，这是一种用于验证以任何硬件描述语言描述的电路的开源工具。它建立在Chisel硬件构造语言的基础之上，并使用Scala通过通用验证方法（UVM）启发并适用于Chisel中描述的设计的测试策略来驱动验证。ChiselVerify是基于三个关键思想而创建的。首先，我们的解决方案通过允许在现代化的高级编程环境中进行硬件测试，极大地提高了验证工程师的工作效率。第二，得益于Chisel黑盒的灵活性，该框架可以使用任何硬件描述语言运行。最后，该解决方案已很好地集成到现有的Chisel领域中，使其成为当前现有测试库的扩展。我们以受SystemVerilog中发现的功能启发的方式实施ChiselVerify。这样一来，您就可以使用功能覆盖率，