This paper presents a fully integrated three-way Doherty architecture to address the challenges of 5G applications using laterally-diffused metal-oxide semiconductor (LDMOS) technology. By using the so-called CDS cancelation method for the Doherty combiner design, a wideband impedance transformation is achieved, that combined with the three-way Doherty power amplifier (DPA) architecture allows for high efficiency in deep back-off, with a reduced load modulation for high bandwidth. Throughout this paper, the design approach and realization are described, while multiple critical design challenges will be addressed such as low frequency drain resonance optimization, impact of in-package coupling effects, and linearity versus efficiency tradeoff. Two state-of-the-art three-way fully integrated LDMOS DPA monolithic microwave integrated circuit (MMICs) are presented to demonstrate how these measures have been successfully applied to different power amplifier (PA) line-up components for 5G base station systems. First, a 60 W 1.8–2.2 GHz multi-stage device for driver application in true dual-band operation is presented. The circuit design pays special attention to extended PA video bandwidth thanks to integrated passive device. After digital pre-distortion (DPD) in dual-band operation, this highly linear device achieves an outstanding adjacent channel leakage ratio (ACLR) of −56 dBc for a 2cLTE 20 MHz 8 dB peak-to-average ratio signal spaced by 345 MHz, thus 385 MHz instantaneous bandwidth (IBW), with 29% efficiency at 35 dBm, 12 dB output back-off (OBO). Second, the simulation and measurement results of a 55 W 2.6 GHz multi-stage DPA for massive-MIMO final stage application are presented, which yields an excellent linearized efficiency of 49% using a 200 MHz 10cLTE signal with an ACLR lower than −47.5 dBc. For 8cLTE 20 MHz (160 MHz IBW), the device yields 50% efficiency with −50.7 dBc ACLR linearized after DPD. The achieved efficiency is well comparable to published GaN DPAs. These results were achieved by improved simulation techniques to minimize frequency dispersion and thus allow high efficiency operation over wide bandwidth. Both devices show that LDMOS is not only a mature technology which allows those PAs to be reliable and low-cost for mass production in very compact packages, but also provide best-in-class RF performance according to the needs of 5G base station systems.

中文翻译：

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完全集成的三路 LDMOS Doherty PA，适用于 1.8–2.2 GHz 双频和 2.6 GHz m-MIMO 5G 应用

本文介绍了一种完全集成的三路 Doherty 架构，以使用横向扩散金属氧化物半导体 (LDMOS) 技术应对 5G 应用的挑战。通过使用所谓的CDSDoherty 组合器设计的抵消方法，实现了宽带阻抗变换，与三路 Doherty 功率放大器 (DPA) 架构相结合，可在深度回退中实现高效率，同时减少负载调制以实现高带宽。在本文中，描述了设计方法和实现，同时将解决多个关键设计挑战，例如低频漏极谐振优化、封装内耦合效应的影响以及线性与效率的权衡。介绍了两种最先进的三路全集成 LDMOS DPA 单片微波集成电路 (MMIC)，以展示这些措施如何成功应用于 5G 基站系统的不同功率放大器 (PA) 阵容组件。首先，60 W 1.8–2。介绍了用于真正双频操作中的驱动器应用的 2 GHz 多级器件。由于集成了无源器件，电路设计特别注意扩展 PA 视频带宽。在双频操作中进行数字预失真 (DPD) 之后，对于间隔为 345 MHz 的 2cLTE 20 MHz 8 dB 峰均比信号，这款高线性器件可实现 -56 dBc 的出色邻道泄漏比 (ACLR) ，因此 385 MHz 瞬时带宽 (IBW)，在 35 dBm 时效率为 29%，输出回退 (OBO) 为 12 dB。其次，展示了用于大规模 MIMO 末级应用的 55 W 2.6 GHz 多级 DPA 的仿真和测量结果，使用 200 MHz 10cLTE 信号产生 49% 的出色线性化效率，ACLR 低于 -47.5 dBc . 对于 8cLTE 20 MHz（160 MHz IBW），该器件产生 50% 的效率，在 DPD 之后线性化为 -50.7 dBc ACLR。实现的效率与已发布的 GaN DPA 相当。这些结果是通过改进的模拟技术来实现的，以最大限度地减少频率色散，从而在宽带宽上实现高效运行。这两款器件都表明，LDMOS 不仅是一项成熟的技术，可以让这些功率放大器在非常紧凑的封装中可靠且低成本地进行大规模生产，而且还可以根据 5G 基站系统的需求提供一流的射频性能。