This work investigates the reliability assessment of high-k spacer and the effect of temperature on the device analog/RF performance for Inverted ‘T' (IT) Junctionless (JL) FinFET. A systematic analysis is performed for different high-k spacer materials, like, SiO₂, Si₃N₄, and HfO₂ to improve the analog/RF performances. This work also represents the effect of oxide stacking i.e., low-k on high-k materials as a spacer to ensure device reliability for analog/RF performance. Various performances as subthreshold swing (SS), current switching ratio (I_ON/I_OFF ratio), drain induced barrier lowering (DIBL), transconductance (g_m), early voltage (V_EA), gain (A_V), higher order derivatives of current (g_m1, g_m2, g_m3), Capacitance (C_GS, C_GD, C_GG), cut-off frequency (f_T), 2nd and 3rd order voltage intercept point (VIP₂, VIP₃), 3rd order intermodulation input intercept point (IIP₃) are analyzed for the device. The obtained results are achieved with uniform high doping concentration under bulk conduction mechanism which downsizes the short channel effects and thereby enhances the linearity FoMs for analog/RF circuit applications. At 300 K, the acquire SCEs for high-k spacers, for example, SS, I_ON/I_OFF ratio, DIBL accomplish to be 64 mV/decade, 10⁷, 26 mV/V respectively. In contrast with distinctive temperature variation from 200 K to 400 K, the SCEs at 300 K are same to that of the high-k spacers.

这项工作研究了高k隔离层的可靠性评估以及温度对反相'T'（IT）无结（JL）FinFET器件模拟/ RF性能的影响。针对不同的高k间隔材料（例如SiO ₂，Si ₃ N ₄和HfO ₂）进行了系统分析，以改善模拟/ RF性能。这项工作还代表了氧化物堆叠的影响，即低k在高k材料上作为隔离层，以确保器件具有模拟/ RF性能的可靠性。亚阈值摆幅（SS），电流开关比（I _ON / I _OFF比），漏极引起的势垒降低（DIBL）等各种性能），跨导（g _m），早期电压（V _EA），增益（A _V），电流的高阶导数（g _m1，g _m2，g _m3），电容（C _GS，C _GD，C _GG），切关断频率（f _T），二阶和三阶电压拦截点（VIP ₂，VIP ₃），三阶互调输入拦截点（IIP ₃）进行设备分析。在体传导机制下以均匀的高掺杂浓度实现了所获得的结果，这减小了短沟道效应的尺寸，从而增强了模拟/ RF电路应用的线性FoM。在300 K时，用于高k间隔物的获得的SCE，例如SS，I _ON / I _OFF比，DIBL分别达到64 mV / decade，10 ⁷和26 mV / V。与200 K至400 K的明显温度变化相比，300 K时的SCE与高k垫片的SCE相同。