The proposed booth decoder/encoder unit is an ultrahigh-speed unit among the reported ones which was designed by modifying and creating a new format truth table with 0.18 μm CMOS technology. According to the modified truth table, four cases are defined, and a proper circuit for each case is designed. The proposed structure is discussed considering the possible problems such as the swing and discharge problems. The gate-level delay of the proposed structure and other related works have been calculated and are compared. The propagation delay of the proposed structure has been calculated and simulated to validate the data. To justify the comparisons, other related works have been simulated again with the same condition. The propagation delay of the proposed structure is 226 ps, which is minimum compared to previous related works. The proposed structure reduces the delay by 30–200% comparing related works and also improves the delay of the multiplier 4–21%. The power consumption and the area of the structure are 477 μw and 20 × 18 μm², respectively. In this paper, Hspice software for simulating, MATLAB for numerical calculations, and Cadence for designing the layout of the proposed structure have been used.

中文翻译：

---

用于 Radix-4 Booth 乘法器的新型高速低功耗解码器/编码器

所提出的展位解码器/编码器单元是已报道的超高速单元，它是通过修改和创建采用 0.18 μm CMOS 技术的新格式真值表而设计的。根据修改后的真值表，定义了四种情况，并针对每种情况设计了合适的电路。考虑到可能的问题，如摆动和排放问题，讨论了所提出的结构。已计算并比较了所提出结构和其他相关工作的门级延迟。已计算和模拟所提出结构的传播延迟以验证数据。为了证明比较的合理性，其他相关工作已在相同条件下再次模拟。所提出结构的传播延迟为 226 ps，与之前的相关工作相比，这是最小的。与相关工作相比，所提出的结构将延迟减少了 30-200%，并将乘法器的延迟提高了 4-21%。功耗和结构面积分别为477 μw和20 × 18 μm²、分别。在本文中，Hspice 软件用于模拟，MATLAB 用于数值计算，Cadence 用于设计所提出结构的布局。