Purpose

Multipliers that form the basic building blocks in most of the error-resilient media processing applications are computationally intensive and power-hungry modules. Therefore, improving the multiplier’s performance in terms of area, critical path delay and power has become an important research area. This paper aims to propose two improved multiplier designs based on a new approximate compressor circuit to reduce the hardware complexity at the partial product reduction stage. The proposed approximate 4:2 compressor design significantly reduces the overall hardware cost of the multiplier. The error introduced by the approximate compressor is reduced using a new technique of assigning inputs to the compressors in the partial product reduction structure.

Design/methodology/approach

The multiplier designs implemented using the proposed approximate 4:2 compressor are targeted for error-resilient applications. For fair comparisons, various multiplier designs, including the proposed one, are implemented in MATLAB. The quality analysis is carried out using standard images, and metrics such as structural similarity index are computed to quantify the result of proposed designs with the existing architectures. Next, Verilog gate-level designs are synthesized to compute area, delay and power to prove the efficacy of the proposed designs.

Findings

Exhaustive error and hardware analysis have been carried out for the existing and proposed multiplier architectures. Error analysis carried out using MATLAB proves that the proposed designs achieve better quality metrics than existing designs. Hardware results show that area, the power consumed and critical path delay are reduced up to 39.8%, 51.7% and 15.9%, respectively, compared to the existing designs. Toward the end, the proposed designs impact is quantified and compared with existing designs on real-time image sharpening and image multiplication applications.

Originality/value

The area, delay and power metrics of the multiplier can be improved using an approximate compressor in an error-resilient application. Accordingly, in this work, a new compressor is proposed that reduces the hardware complexity in the multiplier architecture. However, the proposed approximate compressor, while reducing the computational complexity, tends to introduce error in the multiplier. The error introduced by the approximate compressor is reduced using a new technique of assigning inputs to the compressors in the partial product reduction structure. With the help of the approximate compressor and a technique of input realignment, hardware efficient and highly accurate multiplier designs are achieved.

中文翻译：

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用于媒体处理应用的硬件高效近似乘法器架构

目的

在大多数抗错媒体处理应用程序中，构成基本构建块的乘法器是计算密集型和耗电模块。因此，提高乘法器在面积、关键路径延迟和功率方面的性能已成为一个重要的研究领域。本文旨在基于一种新的近似压缩器电路提出两种改进的乘法器设计，以降低部分乘积减少阶段的硬件复杂度。建议的近似 4:2 压缩器设计显着降低了乘法器的整体硬件成本。近似压缩器引入的误差使用一种新技术来减少，该技术将输入分配给部分乘积减少结构中的压缩器。

设计/方法/方法

使用建议的近似 4:2 压缩器实现的乘法器设计是针对容错应用的。为了公平比较，各种乘法器设计，包括所提出的设计，都在 MATLAB 中实现。使用标准图像进行质量分析，计算结构相似性指数等指标，以量化现有架构提出的设计结果。接下来，综合 Verilog 门级设计以计算面积、延迟和功率，以证明所提出设计的有效性。

发现

已经对现有和提议的乘法器架构进行了详尽的误差和硬件分析。使用 MATLAB 进行的误差分析证明，所提出的设计比现有设计实现了更好的质量指标。硬件结果表明，与现有设计相比，面积、功耗和关键路径延迟分别降低了 39.8%、51.7% 和 15.9%。最后，对提出的设计影响进行量化，并与实时图像锐化和图像乘法应用的现有设计进行比较。

原创性/价值

在容错应用中使用近似压缩器可以改善乘法器的面积、延迟和功率指标。因此，在这项工作中，提出了一种新的压缩器，可以降低乘法器架构中的硬件复杂性。然而，所提出的近似压缩器在降低计算复杂度的同时，往往会在乘法器中引入误差。近似压缩器引入的误差使用一种新技术来减少，该技术将输入分配给部分乘积减少结构中的压缩器。在近似压缩器和输入重新对齐技术的帮助下，实现了硬件高效和高精度的乘法器设计。