We propose an experimentally validated physics-based process-induced variability (PIV) aware SPICE simulation framework-enabling the estimation of performance variation due to line-edge-roughness (LER), metal-gate-granularity (MGG), random-dopant-fluctuation (RDF), and oxide-thickness-variation (OTV) at sub-20 nm technology node devices. The framework utilizes LER, RDF, OTV, and MGG defining parameters such as fin-edge correlation coefficient (ρ), autocorrelation length (Λ), grain-size (GS), σ[EOT], etc. as the inputs, and produces Id-Vg distribution of ensemble size 250 as an output. We have validated the framework against 14 nm FinFET experimental data for Id-Vg trends as well as for the threshold-voltage (VT), ON-current (ION), and subthreshold slope (SS) distributions for a range of device dimensions with a reasonably good match. The worst and the best case R square errors are 0.64 and 0.98, respectively, for the validation. The very nature of the proposed framework allows the designers to use it for a vast range of process technologies. Such models are of dual importance, as it enables a PIV aware prediction of circuit-level performance, and provides a platform to estimate PIV parameters efficiently, on-par with sophisticated structural characterization tools.

中文翻译：

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适用于 20 纳米以下 FinFET 技术的工艺引起的可变性感知 SPICE 仿真平台的实验验证


我们提出了一种经过实验验证、基于物理的工艺诱发变异性 (PIV) 感知 SPICE 仿真框架，能够估计由于线边缘粗糙度 (LER)、金属栅极粒度 (MGG)、随机掺杂剂而导致的性能变化 - 20 nm 以下技术节点器件的波动（RDF）和氧化物厚度变化（OTV）。该框架利用LER、RDF、OTV和MGG定义鳍边相关系数(ρ)、自相关长度(Λ)、晶粒尺寸(GS)、σ[EOT]等参数作为输入，并产生整体大小为 250 的 Id-Vg 分布作为输出。我们根据 14 nm FinFET 实验数据验证了该框架的 Id-Vg 趋势以及一系列器件尺寸的阈值电压 (VT)、导通电流 (ION) 和亚阈值斜率 (SS) 分布，相当不错的匹配。对于验证，最坏和最好情况下的 R 平方误差分别为 0.64 和 0.98。所提出的框架的本质允许设计者将其用于广泛的工艺技术。此类模型具有双重重要性，因为它能够对电路级性能进行 PIV 感知预测，并提供一个有效估计 PIV 参数的平台，与复杂的结构表征工具相当。