The dynamic avalanche reliability of 1200-V silicon carbide (SiC) power metal-oxide semiconductor field-effect transistors (MOSFETs) is studied in this article. The unclamped inductive switching (UIS) tests are conducted to locate failure points. An optimized thermal network model with the definition of the material above the epitaxial layer is used to simulate the avalanche process of SiC MOSFETs. The simulation and experiment results are matched, which verifies the validity of this model. Further simulation results show that a slight change in the doping profile of the p-well region will make the avalanche capability significantly different. Then, the effect of the deviation in cell parameters on the avalanche capability is studied by multicell simulation. The results demonstrate that uneven distribution of internal parameters makes the parasitic bipolar junction transistor (BJT) of some cells turn-on first, causing a significant concentration of current and heat in a very short time, and eventually forming hot spots often observed in failed devices.

中文翻译：

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通过优化热电模拟研究1200V SiC MOSFET的单脉冲雪崩故障

本文研究了1200V碳化硅（SiC）功率金属氧化物半导体场效应晶体管（MOSFET）的动态雪崩可靠性。进行非钳位电感开关（UIS）测试以定位故障点。使用外延层上方材料定义的优化热网络模型来模拟SiC MOSFET的雪崩过程。仿真结果与实验结果相吻合，验证了该模型的有效性。进一步的仿真结果表明，p阱区掺杂分布的轻微变化将使雪崩能力显着不同。然后，通过多单元仿真研究了单元参数偏差对雪崩能力的影响。