A 5-bit active digital step attenuator (DSA), which simultaneously achieves low amplitude and phase variations, is proposed for wideband phased-array applications. The input and output impedances for each attenuation unit under the reference state and the attenuation state can remain basically the same. Therefore, the amplitude and phase errors caused by a load impedance mismatch between each unit can be alleviated. Implemented in 130-nm silicon–germanium (SiGe) BiCMOS technology platform, the proposed DSA provides a maximum attenuation range of 15.5 dB with 0.5-dB steps. It exhibits an insertion loss (IL) less than 13 dB and input/output return losses less than −10 dB from 31 to 41 GHz. In addition, with the help of minimized amplitude and phase variations, the DSA exhibits a root-mean-square (rms) amplitude error less than 0.2 dB and an rms phase error less than 2.5° at 33–41 GHz, which are the lowest such errors ever reported. The chip core area of the DSA is 0.22 mm ² (0.5 mm $\times0.44$ mm). It shows a suitable performance for 5G applications.

中文翻译：

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具有最小单位阻抗变化的33–41GHz SiGe-BiCMOS数字步进衰减器

针对宽带相控阵应用，提出了一种同时实现低幅度和相位变化的5位有源数字步进衰减器（DSA）。在参考状态和衰减状态下，每个衰减单元的输入和输出阻抗可以基本保持相同。因此，可以减轻由每个单元之间的负载阻抗失配引起的幅度和相位误差。拟议的DSA在130 nm的硅锗（SiGe）BiCMOS技术平台中实施，以0.5 dB的步长提供了15.5 dB的最大衰减范围。在31至41 GHz频率范围内，它的插入损耗（IL）小于13 dB，输入/输出回波损耗小于-10 dB。此外，借助最小化幅度和相位变化，DSA的均方根（rms）幅度误差小于0。在33–41 GHz频率下2 dB的均方根相位误差小于2.5°，这是有史以来最低的此类误差。DSA的芯片核心面积为0.22 mm ²（0.5毫米 $ \ times0.44 $ 毫米）。它显示了适合5G应用的性能。