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Low-Power Vertical Tunnel Field-Effect Transistor Ternary Inverter
IEEE Journal of the Electron Devices Society ( IF 2.0 ) Pub Date : 2021-02-05 , DOI: 10.1109/jeds.2021.3057456
Hyun Woo Kim , Daewoong Kwon

In this study, vertical tunnel FET-based ternary CMOS (T-CMOS) is introduced and its electrical characteristics are investigated using TCAD device and mixed-mode simulations with experimentally calibrated tunneling parameters. This new T-CMOS utilizes two different types of tunneling currents to form three different output voltage states: (1) source-to-drain tunneling current; and (2) conventional source-to-channel tunneling current. To form a half supply voltage ( $\text{V}_{DD}$ ) output voltage during the inverter operation, the n-/p-type devices of the proposed T-CMOS are designed to have constant source-to-drain tunneling current regardless of gate voltage ( $\text{V}_{GS}$ ) by using nitride spacer between gate and drain. Also, typical binary inverter operation is performed using the source-to-channel tunneling. In voltage transfer characteristics (VTC), it is confirmed that there is the clear half $\text{V}_{DD}$ state after matching the tunneling currents of the n-/p-type devices. It is revealed that the stable half $\text{V}_{DD}$ state cannot be achievable if the currents are mismatched by gate workfunction, gate dielectric thickness, and interface trap variations, implying that the current matching between n-/p-type devices is crucial to obtain stable ternary operations.

中文翻译:

低功率垂直隧道场效应晶体管三元逆变器

在这项研究中,介绍了基于垂直隧道FET的三元CMOS(T-CMOS),并使用TCAD器件和具有实验校准隧道参数的混合模式仿真研究了其电特性。这种新的T-CMOS利用两种不同类型的隧穿电流来形成三种不同的输出电压状态:(1)源到漏隧穿电流;(2)传统的源到通道隧穿电流。形成一半的电源电压( $ \ text {V} _ {DD} $ )在逆变器操作期间的输出电压上,建议的T-CMOS的n / p型器件被设计为具有恒定的源极到漏极隧穿电流,而与栅极电压无关( $ \ text {V} _ {GS} $ )在栅极和漏极之间使用氮化物隔离层。而且,典型的二进制逆变器操作是使用源到通道隧道技术执行的。在电压传输特性(VTC)中,确认存在清晰的一半 $ \ text {V} _ {DD} $ 匹配n- / p型器件的隧道电流之后的状态。据透露,稳定的一半 $ \ text {V} _ {DD} $ 如果电流因栅极功函数,栅极介电层厚度和界面陷阱变化而失配,则无法实现该状态,这意味着n / p型器件之间的电流匹配对于获得稳定的三元操作至关重要。
更新日期:2021-02-26
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