This article presents a fully integrated gesture and gait classification system-on-chip (SoC) for rehabilitation application. In order to reduce the power consumption and area cost on the analog front end, special analog-to-digital converter (ADC)-less mixed-signal feature extraction (MSFE) circuits were designed to directly generate eight commonly used time-domain features to eliminate the area cost of ADC. A fully connected neural network classifier was implemented supporting: 1) on-chip learning to deliver user-specific training for better classification accuracy; 2) dedicated neural network layer to support gait classification; and 3) multi-chip data communication, which transfers only low-dimensional features from the neural network to minimize the communication bottleneck in a sensor fusion environment. A 12-channel test chip was fabricated in a 65-nm low-power process to demonstrate the proposed techniques. The measurements show an average power of $1~\mu \text{W}$ per channel and a 3-ms computational latency as required by the stringent rehabilitation requirement. In addition, the MSFE circuits achieve $3\times $ saving of area compared with the conventional approach, while the communication bandwidth was reduced by $100\times $ due to the transferring of only low-dimensional feature data from the neural network among multiple chips.

中文翻译：

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用于使用ADC少混合信号特征提取和训练能力的神经网络分类器进行修复的手势分类SoC

本文介绍了用于康复应用的完全集成的手势和步态分类系统芯片（SoC）。为了降低模拟前端的功耗和面积成本，设计了特殊的无模数转换器（ADC）的混合信号特征提取（MSFE）电路，以直接生成八个常用的时域特征，以降低功耗。消除了ADC的面积成本。实现了完全连接的神经网络分类器，该分类器支持：1）片上学习，以提供针对特定用户的培训，以实现更好的分类准确性；2）专用的神经网络层支持步态分类；3）多芯片数据通信，仅传递来自神经网络的低维特征，以最小化传感器融合环境中的通信瓶颈。以65纳米低功耗工艺制造了12通道测试芯片，以演示所提出的技术。测量结果显示平均功率为 $ 1〜\ mu \ text {W} $ 严格的恢复要求所要求的每个通道和3毫秒的计算延迟。此外，MSFE电路可实现 $ 3 \次$ 与传统方法相比节省了面积，而通信带宽却减少了 $ 100 \次$ 由于在多个芯片之间仅从神经网络传输低维特征数据。