Future computing architectures will host increasing numbers of cores while also moving toward specialized architectures and accelerators. This development strains hardware and software design, verification, and system validation efforts. This letter introduces a virtual platform (VP) centered design flow that not only enables early software development but also considers a solution for the challenges on hardware and system level. As a core element, a hybrid prototyping framework targeting networks-on-chip (NoC) links for interfacing a VP and a field-programmable gate array provides scalability and accuracy for hardware verification and system validation.

中文翻译：

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以虚拟平台为中心的设计和验证流程中的混合原型框架


未来的计算架构将容纳越来越多的核心，同时也朝着专用架构和加速器的方向发展。这种开发给硬件和软件设计、验证和系统验证工作带来了压力。这封信介绍了一种以虚拟平台 (VP) 为中心的设计流程，该流程不仅支持早期软件开发，而且还考虑了针对硬件和系统级别挑战的解决方案。作为核心元素，混合原型框架针对用于连接 VP 和现场可编程门阵列的片上网络 (NoC) 链路，为硬件验证和系统验证提供了可扩展性和准确性。