Three Dimensional Field Programmable Gate Arrays (3D FPGAs) recently are presented as the next generation of the FPGA family to continue the integration of more transistors on a single chip seamlessly. The 3D FPGA are fabricated by stacking several layers of semiconductor substrates and the interconnection among layers are realized using Through Silicon Vias (TSVs). Despite their benefits regarding less area and higher speed, 3D FPGAs encounter two major problems; huge size of single TSV and trapping generated heat in inner layers. To handle these problems, we propose a complete Computer Aided Design (CAD) flow to implement an arbitrary logic circuit on 3D FPGA. Prtitioning, Placement, and Routing are primary stages of the proposed CAD flow. The partitioning and placement stages of the flow are based on Simulated Annealing algorithm. Furthermore, the routing stage is a modified version of the Pathfinder algorithm. Unbalanced SA based partitioning tremendously reduces the required TSVs along with distribution of highly active circuit’s modules on the bottom layers and constructing thermal channels facilitate transferring the generated heat in intermediate layers. Simulation results show more than 60%, 65%, and 23% reduction in TSV count, heat transfer performance, and area respectively, along with 4% increase in critical path delay. In addition, comparison between 2D FPGA and 3D FPGA with our proposed architecture (including 2 tier), shows that the circuit speed increases by 28.61%, and minimum channel width decreases by 30.47%. Finally, the results of comparison between 2-tier and 4-tier in 3D FPGA show that circuit speed and minimum channel width increase by 15.95% and 15.92% in 4-tier, respectively.

作为第三代FPGA系列，最近推出了三维现场可编程门阵列（3D FPGA），以继续在单个芯片上无缝集成更多晶体管。通过堆叠几层半导体基板来制造3D FPGA，并使用硅通孔（TSV）来实现各层之间的互连。尽管3D FPGA具有面积小，速度快的优点，但仍遇到两个主要问题。单个TSV的巨大尺寸和内层产生的热量被捕获。为了解决这些问题，我们提出了完整的计算机辅助设计（CAD）流程，以在3D FPGA上实现任意逻辑电路。打印，放置和路由是建议的CAD流程的主要阶段。流的划分和放置阶段基于模拟退火算法。此外，探路者算法。基于不平衡SA的分区极大地减少了所需的TSV，并在底层上分布了高活性电路模块，并且构建热通道有助于在中间层中传递产生的热量。仿真结果表明，TSV数量，传热性能和面积分别减少了60％，65％和23％以上，同时关键路径延迟增加了4％。此外，将2D FPGA和3D FPGA与我们建议的体系结构（包括2层）进行比较，结果表明电路速度提高了28.61％，最小通道宽度降低了30.47％。最后，在3D FPGA中2层和4层之间的比较结果表明，在4层中，电路速度和最小通道宽度分别增加了15.95％和15.92％。