To enable easy integration of Internet of Things (IoT) sensors with digital very large scale integrtaion (VLSI) circuits, the interface circuits need to operate efficiently even at low power supply voltages, consuming minimum power from the limited onboard supply source. Schmitt triggers have higher noise margins and lower delays as compared to conventional static CMOS logic circuits, at low-voltage levels and hence are being widely used in VLSI sensor applications. Carbon nanotube FETs (CNFETs) have I_ON:I_OFF and I_ON:C_GG ratios significantly greater than the corresponding CMOS devices, and hence they have been acknowledged as viable candidates to replace CMOS devices in ultra-low-power VLSI circuits. This article presents an ultra-low-power CNFET-based Schmitt trigger design, which consumes significantly lower power than the conventional design. The cause of the higher power consumption in conventional CMOS-based Schmitt trigger is the availability of a direct path between V_DD and ground for a longer time duration, during switching. The short-circuit path in the conventional CMOS Schmitt trigger circuit is the result of the design methodology adopted to obtain hysteresis in VTC curve. The threshold voltage of the CNFET can be easily configured by an appropriate selection of its chiral vector. This property of the CNFET has been used in the implementation of a new, simple but effective Schmitt trigger, which minimizes the short-circuit currents, while providing the same hysteresis as that of conventional design. The proposed circuit operates at 0.4 V V_DD to cater for low-voltage levels of VLSI sensor applications. The proposed CNFET-based Schmitt trigger consumes only 0.002 times the power of conventional CMOS Schmitt trigger and operates 56 times faster than the conventional CMOS design. The overall PDP in the proposed CNFET-based Schmitt trigger has been demonstrated to be merely 0.0003% of the PDP in corresponding conventional designs.

中文翻译：

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一种用于 VLSI 传感器应用的基于超低功耗 CNFET 的改进施密特触发器设计

为了实现物联网 (IoT) 传感器与数字超大规模集成 (VLSI) 电路的轻松集成，接口电路需要即使在低电源电压下也能高效运行，从有限的板载电源消耗最少的功率。与传统静态 CMOS 逻辑电路相比，施密特触发器在低电压电平下具有更高的噪声容限和更低的延迟，因此被广泛用于 VLSI 传感器应用。碳纳米管 FET (CNFET) 具有I _ON : I _OFF和I _ON : C _GG比率明显高于相应的 CMOS 器件，因此它们被认为是替代超低功耗 VLSI 电路中 CMOS 器件的可行候选者。本文介绍了一种基于 CNFET 的超低功耗施密特触发器设计，其功耗明显低于传统设计。传统基于 CMOS 的施密特触发器功耗较高的原因是V _DD之间的直接路径的可用性并在开关期间接地更长的时间。传统 CMOS 施密特触发器电路中的短路路径是为获得 VTC 曲线滞后所采用的设计方法的结果。The threshold voltage of the CNFET can be easily configured by an appropriate selection of its chiral vector. CNFET 的这一特性已用于实现一种新的、简单但有效的施密特触发器，该触发器将短路电流降至最低，同时提供与传统设计相同的迟滞。建议的电路工作在 0.4 V V _DD以满足低电压水平的 VLSI 传感器应用。所提出的基于 CNFET 的施密特触发器的功耗仅为传统 CMOS 施密特触发器的 0.002 倍，并且运行速度是传统 CMOS 设计的 56 倍。所提出的基于 CNFET 的施密特触发器中的整体 PDP 已被证明仅为相应传统设计中 PDP 的 0.0003%。