We present Calyx, a new intermediate language (IL) for compiling high-level programs into hardware designs. Calyx combines a hardware-like structural language with a software-like control flow representation with loops and conditionals. This split representation enables a new class of hardware-focused optimizations that require both structural and control flow information which are crucial for high-level programming models for hardware design. The Calyx compiler lowers control flow constructs using finite-state machines and generates synthesizable hardware descriptions. We have implemented Calyx in an optimizing compiler that translates high-level programs to hardware. We demonstrate Calyx using two DSL-to-RTL compilers, a systolic array generator and one for a recent imperative accelerator language, and compare them to equivalent designs generated using high-level synthesis (HLS). The systolic arrays are $4.6\times$ faster and $1.1\times$ larger on average than HLS implementations, and the HLS-like imperative language compiler is within a few factors of a highly optimized commercial HLS toolchain. We also describe three optimizations implemented in the Calyx compiler.

中文翻译：

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加速器生成器的编译器基础结构

我们介绍Calyx，这是一种新的中间语言（IL），用于将高级程序编译到硬件设计中。Calyx将类似硬件的结构语言与类似软件的带有循环和条件的控制流表示形式相结合。这种拆分表示形式实现了新一类的以硬件为中心的优化，这些优化需要结构和控制流信息，这对于硬件设计的高级编程模型至关重要。Calyx编译器使用有限状态机降低控制流的构造，并生成可综合的硬件描述。我们已经在优化编译器中实现了Calyx，该编译器将高级程序转换为硬件。我们使用两种DSL-to-RTL编译器，一个脉动数组生成器和一种用于最新命令式加速器语言的Calyx进行了演示，并将它们与使用高级综合（HLS）生成的等效设计进行比较。与HLS实现相比，脉动阵列的速度平均快了4.6倍，平均快了1.1倍，并且类似HLS的命令式语言编译器处于高度优化的商业HLS工具链的几个因素之内。我们还将描述在Calyx编译器中实现的三种优化。