High power consumption of Field-Programmable Gate Arrays (FPGAs) makes them a less attractive choice for ultra-low-power applications. Depending on the power source, ultra-low-power systems could either be constrained by power (energy harvesting systems) or by energy (battery-powered systems). In this work, we are evaluating four different FPGA tiles to find the one that is better suited for both power-constrained and energy-constrained systems. Ultra-low-power systems apply voltage downscaling to reduce the power consumption. However, the operational limits of different blocks do not allow conventional FPGA to be operated at very low voltage. Therefore, their logic capacity can only be increased by 2–4 times by applying voltage downscaling. In this work, we identified the blocks in FPGA tiles that are vulnerable at low voltage and replace them with alternate circuits. The results indicate that, by slight modifications in the conventional FPGA tiles, logic capacity can be increased up to 8 times, whereas power-delay-product can be reduced up to 74%.

现场可编程门阵列（FPGA）的高功耗使其成为超低功耗应用的吸引力较小的选择。根据电源的不同，超低功耗系统可能受到功率（能量收集系统）或能量（电池供电系统）的约束。在这项工作中，我们正在评估四个不同的FPGA磁贴，以找到一个更适合功率受限和能量受限的系统。超低功耗系统通过降低电压比例来降低功耗。但是，不同模块的操作限制不允许传统的FPGA在非常低的电压下运行。因此，通过施加电压缩小比例，它们的逻辑容量只能增加2-4倍。在这项工作中，我们在FPGA磁贴中确定了在低电压下易受攻击的模块，并用备用电路替换了它们。结果表明，通过对常规FPGA磁贴进行稍加修改，逻辑容量最多可以增加8倍，而功率延迟乘积最多可以减少74％。