This paper presents a new multiple-time programmable (MTP) memory cell that features an n-well as the erasing gate and is implemented in a 16nm FinFET technology process. It is composed of slot contacts placed beside a metal gate for lateral coupling to the floating gate, while an n-well with a floating gate laid on top of it functions as erasing terminal. With adjusted slot contact length, a programming gate (PG) coupling ratio can be designed for the optimized program, erase and read operations to best meet the needs for logic non-volatile memory array development. An increase in the PG coupling ratio provides an increasing read current and lower leakage current, which brings about an improved read window in a larger array. Good endurance test results and disturb immunity were also demonstrated on these new MPT cells.

本文介绍了一种新型多次可编程 (MTP) 存储单元，该存储单元采用 n 阱作为擦除栅极，并采用 16 纳米 FinFET 技术工艺实现。它由放置在金属栅极旁边的槽触点组成，用于横向耦合到浮栅，而在其顶部放置浮栅的 n 阱用作擦除端子。通过调整槽接触长度，可以针对优化的编程、擦除和读取操作设计编程门（PG）耦合比，以最好地满足逻辑非易失性存储器阵列开发的需求。PG 耦合比的增加提供了增加的读取电流和更低的泄漏电流，这在更大的阵列中带来了改进的读取窗口。这些新的 MPT 电池也证明了良好的耐力测试结果和干扰免疫力。