The power amplifiers (PAs) are generally the most power-consuming building blocks in Radio Frequency (RF) transceivers. This paper presents a high efficiency fully integrated inverse class D power amplifier for the narrowband Internet of Things (NB-IoT) applications. In this design, the PA's power added efficiency (PAE) is improved by inserting two auxiliary PMOS transistors into the conventional topology of class D⁻¹ PA, and the chip area is reduced by proper selection of the RF choke. An on-chip balun is designed to combine the output power of the two transistors, while its primary equivalent inductor resonates with a capacitor at the fundamental frequency. Based on simulation results, the proposed PA achieves 16.5 dBm output power with a peak power added efficiency (PAE) of 51.3%, while operating from a 1-V supply. Moreover, the proposed PA demonstrates the power gain of 21.6 dB and drain efficiency of 57% at the frequency band of 1.85–1.91 GHz. By using 180 nm TSMC technology, the proposed PA occupies a total chip area of 1.19 mm² (0.85 mm × 1.4 mm), including pads.

功率放大器（PA）通常是射频（RF）收发器中最耗电的构件。本文提出了一种适用于窄带物联网（NB-IoT）应用的高效，完全集成的D类逆功率放大器。在此设计中，通过将两个辅助PMOS晶体管插入D ^-1级传统拓扑中，可以提高PA的功率附加效率（PAE）PA，并且芯片面积由RF扼流圈的适当选择降低。片内平衡-不平衡变换器被设计为组合两个晶体管的输出功率，而其初级等效电感器则与电容器在基频处谐振。根据仿真结果，建议的PA在使用1V电源工作时，可实现16.5 dBm的输出功率，峰值功率附加效率（PAE）为51.3％。此外，拟议的功率放大器在1.85–1.91 GHz频带上具有21.6 dB的功率增益和57％的漏极效率。通过使用180 nm TSMC技术，拟议的PA占据了包括焊盘在内的芯片总面积为1.19 mm ²（0.85 mm×1.4 mm）。