The total ionization dose (TID) effect and negative bias temperature instability (NBTI) effect of 130-nm partially-depleted silicon-on-insulator (PDSOI) MOSFETs fabricated on hardened wafers with silicon ion implantation and unhardened wafers are investigated. A TID-hardened PDSOI MOSFET up to 1 Mrad(Si) is obtained by Si+ implantation in buried oxide (BOX). The hardening benefits from the electron traps in the BOX introduced by Si+ implantation. Although the radiation hardening process has a rare impact on nominal electrical characteristics of the device before irradiation, it will affect the NBTI reliability, which is manifested as the decrease in the NBTI lifetime for the radiation-hardened devices. The energy distribution of positive charges built up during NBTI stress is obtained. It proves that more damage-related traps exist near the gate oxide/silicon interface for the radiation-hardened device, which accelerates the threshold voltage shift during the NBTI stress. This conclusion is also verified by the low-frequency noise characteristics.

中文翻译：

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埋入氧化物 Si+ 注入对 PDSOI MOSFET TID 和 NBTI 效应的影响


研究了在硅离子注入硬化晶圆和未硬化晶圆上制造的 130 nm 部分耗尽绝缘体上硅 (PDSOI) MOSFET 的总电离剂量 (TID) 效应和负偏压温度不稳定性 (NBTI) 效应。通过在埋层氧化物 (BOX) 中注入 Si+，可以获得高达 1 Mrad(Si) 的 TID 硬化 PDSOI MOSFET。硬化受益于 Si+ 注入引入的 BOX 中的电子陷阱。尽管辐射硬化工艺对辐照前器件的标称电气特性影响很小，但它会影响 NBTI 可靠性，表现为辐射硬化器件 NBTI 寿命的降低。获得了 NBTI 应力期间建立的正电荷的能量分布。结果证明，抗辐射器件的栅极氧化物/硅界面附近存在更多与损伤相关的陷阱，这加速了 NBTI 应力期间的阈值电压漂移。低频噪声特性也验证了这一结论。