In this paper, we present GradPIM, a processing-in-memory architecture which accelerates parameter updates of deep neural networks training. As one of processing-in-memory techniques that could be realized in the near future, we propose an incremental, simple architectural design that does not invade the existing memory protocol. Extending DDR4 SDRAM to utilize bank-group parallelism makes our operation designs in processing-in-memory (PIM) module efficient in terms of hardware cost and performance. Our experimental results show that the proposed architecture can improve the performance of DNN training and greatly reduce memory bandwidth requirement while posing only a minimal amount of overhead to the protocol and DRAM area.

中文翻译：

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GradPIM：一种用于梯度下降的实用的DRAM处理架构

在本文中，我们介绍了GradPIM，它是一种内存中处理架构，可加速深度神经网络训练的参数更新。作为可以在不久的将来实现的内存中处理技术之一，我们提出了一种不侵犯现有内存协议的增量，简单的体系结构设计。扩展DDR4 SDRAM以利用存储体组并行性，使我们在内存处理（PIM）模块中的操作设计在硬件成本和性能方面高效。我们的实验结果表明，提出的体系结构可以提高DNN训练的性能，并大大减少内存带宽需求，同时仅对协议和DRAM区域造成最少的开销。