Two-dimensional (2D) semiconducting materials, in particular transition-metal dichalcogenides, have emerged as the preferred channel materials for sub-5 nm field-effect transistors (FETs). However, the lack of practical doping techniques for these materials poses a significant challenge to designing complementary logic gates containing both n- and p-type FETs. Although electrical tuning of the polarity of 2D-FETs can potentially circumvent this problem, such devices suffer from the lack of balanced n- and p-mode transistor performance, forming one of the most enigmatic challenges of the reconfigurable 2D-FET technology. Here we provide a solution to this dilemma by judicious use of van der Waals (vdW) materials consisting of conductors, dielectrics and semiconductors forming a 50 nm thin quantum engineered strata that can guarantee a purely vdW-type interlayer interaction, which faithfully preserves the mid-gap contact design and thereby achieves an intrinsically mode-balanced and fully reconfigurable all-2D logic gate. The intrinsically mode-balanced gate eliminates the need for transistor sizing and allows post-fabrication reconfigurability to the transistor operation mode, simultaneously allowing an ultra-compact footprint and increased circuit functionality, which can be potentially exploited to build more area-efficient and low-cost integrated electronics for the internet of things (IoT) paradigm.

二维（2D）半导体材料，尤其是过渡金属二卤化物已经出现，成为亚5纳米以下场效应晶体管（FET）的首选沟道材料。但是，对于这些材料缺乏实用的掺杂技术对设计包含n型和p型FET的互补逻辑门构成了重大挑战。尽管对2D-FET的极性进行电调谐可以潜在地解决此问题，但此类设备仍缺乏平衡的n-和p模晶体管的性能，这构成了可重构2D-FET技术的最大难题之一。在这里，我们通过明智地使用由导体，电介质和半导体组成的范德华（vdW）材料，形成50 nm的薄量子工程化层，来保证纯vdW型层间相互作用，从而忠实地保留中间层-间隙接触设计，从而实现了固有的模式平衡和完全可重新配置的全2D逻辑门。固有的模式平衡栅极消除了对晶体管尺寸的需求，并允许制造后重新配置为晶体管工作模式，同时实现了超紧凑的占位面积和增强的电路功能，物联网（IoT）范例。