This research article proposes high-performance square-root carry select adder (SQRT CSLA) architectures with high speed, area and energy efficiency when compared to the existing SQRT CSLA architectures. The first proposed method uses an optimized design of binary to excess-1 converter (BEC)-based SQRT CSLA by incorporating a carry enable binary to excess-1 converter (CEBEC) design that exploits a new logic optimization on the carry propagation path to improve speed of operation, area and energy efficiency. The second proposed method is an optimized design of the regular SQRT CSLA by employing the carry enable and add-one ripple carry adder (ARCA) architectures to decrease the number of gates. Simulation results show that the proposed CEBEC SQRT CSLA offers a savings of 22.81%, 9.95%, 7.95% and 3.98% on area, 14.50%, 5.21%, 3.72% and 3.11% in power consumption and offers 6.78%, 15.46%, 6.57% and 3.83% lesser delay, 20.33%, 19.92%, 10.09% and 6.89% lesser PDP, 28%, 23.85%, 13.78% and 7.58% lesser ADP than the existing regular, BEC SQRT CSLA, SQRT CSLA1 and SQRT CSLA2 architectures. The proposed ARCA SQRT CSLA architecture exhibits 9.26%, 17.71%, 9.06% and 6.39% lesser delay than the existing regular, BEC SQRT CSLA, SQRT CSLA1 and SQRT CSLA2 architectures.

与现有的SQRT CSLA体系结构相比，本文提出了一种具有高速，面积和能源效率的高性能平方根进位选择加法器（SQRT CSLA）体系结构。第一个提出的方法通过结合进位使能二进制到过分1转换器（CEBEC）设计，使用了基于二进制至过1转换器（BEC）的SQRT CSLA的优化设计，该设计在进位传播路径上采用了新的逻辑优化来改进运作速度，面积和能源效率。第二种建议方法是通过采用进位使能和加一纹波进位加法器（ARCA）架构来减少门数，从而对常规SQRT CSLA进行优化设计。仿真结果表明，拟议的CEBEC SQRT CSLA分别节省了22.81％，9.95％，7.95％和3.98％的面积，14.50％，5.21％，3.72％和3。功耗降低11％，延迟降低6.78％，15.46％，6.57％和3.83％，PDP降低20.33％，19.92％，10.09％和6.89％，ADP降低28％，23.85％，13.78％和7.58％现有的常规BEC SQRT CSLA，SQRT CSLA1和SQRT CSLA2体系结构。与现有的常规BEC SQRT CSLA，SQRT CSLA1和SQRT CSLA2体系结构相比，拟议的ARCA SQRT CSLA体系结构的延迟减少了9.26％，17.71％，9.06％和6.39％。