With the rapid growth of computational intelligence techniques, automatic age estimation has achieved efficiency and accuracy that benefited IC aging-mitigation applications. This paper proposes an adaptive anti-aging system scheme that uses an intelligent algorithm to monitor the frequency degradation of digital circuits. An on-chip reliability sensor with voltage controlled oscillator (VCO) architecture achieved the circuit's aging rate, featuring real-time monitoring and tolerance against PVT variations. Cuckoo intelligence-based algorithm with global search strategy could obtain the accuracy data, reduce the number of iterations, and improve use self-adjust efficiency. The loop circuit can be quickly corrected by precise voltage compensation to alleviate performance degradation. The test chip was fabricated in the TSMC 65-nm CMOS technology with a core area of 0.97 mm². The measurement results show that the resolution is 0.004% at 1.2 V and 27 °C and a self-adjust time (SAT) reaches about 1.8 μs with an operating frequency of 500 MHz, recovering at 10% aging-related degradation. In comparison with other related literatures, the resolution of the proposed method is improved by more than 2.5 times.

随着计算智能技术的飞速发展，自动年龄估计已经实现了效率和准确性，这使IC老化缓解应用受益。本文提出了一种自适应的抗衰老系统方案，该方案使用一种智能算法来监视数字电路的频率衰减。具有压控振荡器（VCO）架构的片上可靠性传感器实现了电路的老化率，具有实时监控功能和对PVT变化的容忍度。具有全局搜索策略的基于杜鹃智能的算法可以获取精度数据，减少迭代次数，提高使用自我调整效率。可以通过精确的电压补偿来快速校正环路，以减轻性能下降。²。测量结果表明，在1.2 V和27°C下，分辨率为0.004％，自调整时间（SAT）在工作频率为500 MHz时达到约1.8μs，并在老化引起的10％退化下恢复。与其他相关文献相比，该方法的分辨率提高了2.5倍以上。